研究生: |
楊晏琪 Yang, Yen-Chi |
---|---|
論文名稱: |
應用於突變式分析以基因演算法為基礎的向量產生的方法 Genetic Algorithm-based Pattern Generation for Mutation Analysis |
指導教授: |
王俊堯
Wang, Chun-Yao |
口試委員: |
溫宏斌
Wen, Charles H.-P. 劉建男 Liu, Chien-Nan |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 資訊工程學系 Computer Science |
論文出版年: | 2012 |
畢業學年度: | 100 |
語文別: | 英文 |
論文頁數: | 23 |
中文關鍵詞: | 突變式分析 、產生測試向量 、驗證 |
外文關鍵詞: | mutation, pattern generation, verification |
相關次數: | 點閱:2 下載:0 |
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突變式分析法 (Mutation Analysis) 屬於一種基於錯誤的模擬法。我們將程式裡簡單的語意的改變稱為錯誤(mutant) ,並且針對程式裡的這些錯誤作偵測,透過測試向量的品質以衡量驗證環境。在程式裡一個潛在的錯誤(living mutant)意味著這個錯誤效應無法在電路的輸出端被觀察到。由於暫存器轉移層(RTL)裡複雜的條件式以及較大的變數導致電路裡面存在一些潛在的錯誤。之前和突變式分析法相關的研究主要著重在模擬過程中減少成本,然而,只有少數的研究著致力於產生測試向量以偵測這些錯誤。這篇論文提出了以基因演算法產生測試向量以偵測電路中的錯誤,因而改善驗證環境的品質。在我們的實驗裡,我們以邏輯閘層(gate-level netlist)上沒有被偵測到的錯誤(fault)當成暫存器轉移層上的錯誤,我們透過以PODEM 實作的測試向量自動產生器(ATPG)來產生邏輯閘層上那些很難被偵測到的錯誤。實驗結果顯示我們的方法可以很有效的產生測試向量以偵測那些很難被偵測到的錯誤。
[1] IWLS 2005 Benchmarks [Online].
Available: http://iwls.org/iwls2005/benchmarks.html
[2] SpringSoft. [Online]. Available:http://www.springsoft.com/
[3] A. Acree, T. Budd, R. DeMillo, R. Lipton, and F. Sayward,“Mutation analysis,”Georgia Institute of Technology, Atlanta, Georgia, Technique Report GIT-ICS-79/08, 1979.
[4] A. Benso, A. Bosio, S. Di Carlo, and R. Mariani,“A functional verification based fault injection environment,”in Proc. Defect and Fault-Tolerance in VLSI
Systems, 2007, pp. 114 - 122.
[5] Y.-H. Chang, C.-Y. Wang, and Y.-A. Chen,“GA2CO: Peak temperature estimation of VLSI circuits, in Proc. Int. SoC Design Conference, 2009, pp. 345 - 348.
[6] R. DeMillo, R. Lipton, and F. Sayward,“ Hints on test data selection: Help for the practicing programmer,”IEEE Trans. Computer, vol. 11, no. 4, pp. 34 - 41, April 1978.
[7] R. DeMillo,“Test adequacy and program mutation,” International Conference on Software Engineering, Pittsburgh, Pennsylvania, May 1989, pp. 355 - 356.
[8] L. Drucker,“Functional coverage metrics-the next frontier,”in EEtimes, Aug. 2002.
[9] A. Gluska,“Coverage-oriented verification of banias,” in Proc. Design Automation
Conference, 2003, pp. 280 - 285.
[10] D. E. Goldberg,“Genetic algorithm in search, optimization, and machine learning, MA: Addison-Wesley, 1989.
[11] R. Hamlet,“Testing programs with the aid of a compiler,”IEEE Trans. Software Engineering, vol. SE-3, no. 4, pp. 279 - 290, July 1977.
[12] N. He, P. Rummer, and D. Kroening,“Test-Case Generation for Embedded Simulink via Formal Concept Analysis,” in Proc. Design Automation Conference, 2011, pp. 224 - 229.
[13] W. Howden,“Weak mutation testing and completeness of test sets,”IEEE Trans. Software Engineering, vol. SE-8, no. 4, pp. 371 - 379, July 1982.
[14] Y. Jia and M. Harman,“An analysis and survey of the development of mutation testing,”IEEE Trans. Software Engineering, vol. 35, no. 6, pp. 1 - 32, 2010.
[15] H.-Y. Lin, C.-Y. Wang, S.-C. Chang, Y.-C. Chen, H.-M. Chou, C.-Y. Huang, Y.-C. Yang, and C.-C. Shen,“A probabilistic analysis method for functional qualification under mutation analysis,”in Proc. Design, Automation and Test in Europe, March 2012, pp. 147 - 152.
[16] J. C. Miller and C. J. Maloney,“Systematic mistake analysis of digital computer programs,” Commun. ACM, vol. 6, pp. 58 - 63, Feb. 1963.
[17] A. Offutt,“The coupling effect: fact or fiction,” ACM SIGSOFT Software Engineering Notes, vol. 14, no. 8, pp. 131 - 140, December 1989.
[18] J. Ouyang and Y. Xie,“Power optimization for FinFET-based circuits using genetic algorithms,”in Proc. Int. SOC Conference, 2008, pp. 211 - 214.
[19] S. Tasiran and K. Keutzer,“Coverage metrics for functional validation of hardware designs,” IEEE Design and Test of Computers, vol. 18, no. 4, pp. 36 - 45,
Jul./Aug. 2001.
[20] F. Vargas, E. Bezerra, and A. Terroso,“Testability Verification of Embedded Systems Based onWeak Mutation Analysis,” in Proc. Int. Workshop on Testing Embedded Core-Based System-Chips, 1999.
[21] H.-P Wen, Li-C. Wang, and K.-T Cheng,“Simulation-based functional test generation for embedded processors,” IEEE Trans. Computer, vol. 55, no. 11, pp. 1335 - 1343, November 2006.
[22] S.-C. Wu, C.-Y. Wang, and Y.-C. Chen,“Novel probabilistic combinational equivalence checking,”IEEE Tran. Very Large Scale Integration Systems, vol. 16, no. 4, pp. 365 - 375, April 2008.