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研究生: 吳吉政
Jei-Zheng Wu
論文名稱: 半導體元件測試排程模式之研究
Modeling the Scheduling for Semiconductor Final Test and an Algorithm for Solving the Empirical Problem
指導教授: 簡禎富
Chen-Fu Chien
口試委員:
學位類別: 碩士
Master
系所名稱: 工學院 - 工業工程與工程管理學系
Department of Industrial Engineering and Engineering Management
論文出版年: 2001
畢業學年度: 89
語文別: 英文
論文頁數: 76
中文關鍵詞: 半導體元件測試排程機台組合遺傳演算法甘特圖
外文關鍵詞: Semiconductor Final Testing, Scheduling, Machine Configuration, Genetic Algorithm, Gannt Chart
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  • 近年來,隨著資訊科技的蓬勃發展與作業研究方法的普遍應用,利用電腦輔助來處理需要大量計算的現場排程問題日漸可行與有效。由於半導體產業的製造流程複雜,使得其有效且可行排程方法的設計十分困難。經由文獻回顧發現:半導體排程相關的研究多數針對半導體前端製造的現場派工與排程問題,較少文獻針對後端製造之排程設計提出實務可行的解決方案。
    本研究根據半導體後端元件測試(Final Testing)生產環境的特性與限制,考量製造環境不穩定、工件的迴流、有限資源、機台最佳組合與同一種產品可以在不同種機台組合上測試等實際狀況,建立半導體元件測試排程問題之最佳化數學模式,並且發展適合實務快速求解需要之啟發式演算法,除此之外,本研究發展半導體元件測試排程之遺傳演算法以提高求解之品質。為了使現場排程人員能夠即時得知排程結果以處理製造環境的不穩定,本研究發展之演算方法皆提供了以甘特圖(Gannt Chart)為基的視覺化排程結果。本研究經由模擬與實驗的比較,發現啟發式演算法與遺傳演算法求解的品質較一般派工法則求解的品質佳,並且發現遺傳演算法實際改善了啟發式演算法。


    Recently, using computers to assist in detailed scheduling becomes more feasible and popular due to high improvement of information technique and operation research. It is very difficult to design an effective and efficient scheduling method for semiconductor manufacturing with complex manufacturing flow. Some researches have focus on scheduling and dispatching for Front-End of semiconductor manufacturing. However, little research has been done for designing practical scheduling methods of Back-End of semiconductor manufacturing. This research considers manufacturing dynamics, jobs recirculation, limited resource, optimized machine configuration, and that the same product can be tested on different types of machines with non-identical efficiency and constructs an optimal mathematical model for semiconductor final testing. Besides, for practical purpose, this research also develops a heuristic and a quality-improved genetic algorithm with procedures graphically representing schedules based on Gannt charts. After simulations and experiments, we find that the proposed heuristic and genetic algorithm perform better than dispatching rule-based heuristics.

    Chapter 1 Introduction 1 1.1 Background, Significance, and Motivation 1 1.2 Research aims 2 1.3 Overview of this thesis 2 Chapter 2 Literatures Review 3 2.1 Semiconductor manufacturing and the flow of final testing 4 2.2 Job shop scheduling problems 7 2.2.1 Scheduling and manufacturing scheduling system 7 2.2.2 Job shop models and common scheduling characteristics and constraints 10 2.2.3 Common data required, objectives, and performance measures for job shop scheduling 14 2.3 Common dispatching rules for scheduling problems 16 2.4 Mathematical models for JSSP 17 2.4.1 Mixed integer programming model 17 2.4.2 Binary integer programming model 20 2.5 Fundamentals of genetic algorithms 22 2.6 Solutions of FTSP 25 Chapter 3 The Scheduling Model and Algorithm 28 3.1 Problem structuring 33 3.2 Mathematical programming model and assignment algorithm for TSSP 35 3.2.1 Mathematical programming model for TSSP 36 3.2.2 Assignment algorithm of TSSP 45 3.3 Greedy algorithm and genetic algorithm of TSSP 47 3.3.1 Greedy algorithm of TSSP 47 3.3.2 Genetic algorithm of TSSP 50 3.4 Illustration 55 3.4.2 Illustration of assignment algorithm 57 3.4.3 Illustration of greedy algorithm 60 Chapter 4 Numerical Study 64 Chapter 5 Conclusion and Future Research 71 References 73

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