隨著積體電路製程技術的進步，所設計的電路日益複雜，而當電路有錯誤或缺陷而無法通過測試時，要精確的找出其問題點也就非常困難，然而若能找到問題點有助於良率的提高。有效率的錯誤診斷工具能夠迅速的剔除不可能有錯或是無法判斷的訊號點，縮小可能錯誤的範圍，而減輕錯誤分析工程師的負擔；也能縮短找出錯誤的時間，儘快的提高良率，以增加產品完成上市的速度。
對於如何找出邏輯電路中產生的錯誤點已經有許多的研究，也有許多不同的方法被提出來。大致可分為因果分析法（Cause-effect analysis）與電路模擬法（Simulation-based analysis）等幾類，而大部分的方法都能在有許多錯誤點的電路中精確的找到一個錯誤點。這篇論文提出一種類似分群組方式的多重錯誤點診斷法，它主要是以試誤模擬（Fault simulation）—屬於電路模擬法—為基礎，及對可能的錯誤點做錯誤值注射（faulty value injection），再分析所得到的錯誤症狀（Syndrome）來決定可能的錯誤訊號點。

我們先做第一階段的快速分析，得到一組少量且較為精確的「可疑質點（Prime candidate）」，餘下的訊號點我們將之分成一堆堆互不影響的群組（Group），再對每個群組做第二階段的分析，在每個群組中找到至少一個錯誤點。實驗結果顯示，在診斷含有５個錯誤點的電路中，經過這種方法處理過後，我們對10個訊號做實體層錯誤分析（Physical layer failing analysis），可以找到3.84個錯誤點。利用這種方法可以比以前的方法找到更多的錯誤點，而且根據不同的錯誤點的分佈還有機會縮短診斷的時間。

It is a difficult task to locate the fault sites in an IC that fails manufacturing test. But knowing where the fault is helps us to find the manufacturing defect and improve the yield. A diagnosis tool can help us to shrink the suspect region and to ease the work of the failure analysis. Several types of diagnosis methodology have been proposed. For full-scan designs with only one fault, the accuracy has been improved significantly. However, the techniques for multiple fault diagnosis remain inadequate so far.
In this thesis, we investigate a multiple-fault diagnosis scheme for combinational circuits or full-scan designs. In our approach, we first target the structurally independent faults based on a concept called “prime candidates”. Then, we perform a grouping algorithm to separate the rest of the suspect region into groups, each of which requires its own single-fault diagnosis process to find one fault. Experimental results on three real designs demonstrate that this approach is able to identify more faults than previous ones. On the average, we identify 3.84 faults in only 10 signal inspections with 5 faults in the chip.

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