對於實現高解碼吞吐量的低密度奇偶檢查碼(Low-Density Parity Check Codes, LDPC codes) 使用最小和演算法(Min-Sum Algorithm, MSA)硬體，傳統數位電路在檢查節點更新(check-node units, CNU)實現找正確的前兩小值以及他們的位置(index)是採用樹狀結構演算法，然而此演算法在多項輸入比較值特別是在找尋第二小值，會對硬體面積以及複雜度產生很大的影響。本篇論文提出將數位域(digital-domain)轉成時域(time-domain)的方式來找尋正確前兩小值，因時域計算相較數位電路可以改善在多筆輸入訊號或長字長(long word length)情況的硬體複雜度，並且也有降低電路延遲(latency)等優點。

然而同樣採取時域計算的ISSCC2013[8]在長字長情況下，數位時域轉換器的硬體面積會有越來越大的趨勢且運算速度會降低。為了增加運算速度以及減少晶片面積，這篇論文亦提出針對各輸入比較訊號的最高位元(Most significant bit, MSB)資料做先行處理：設計出一種分類電路將其分類再將剩餘的數位值轉時域做計算，以此達到減少延遲電路數量的目的。本篇論文為了了減少設計的複雜度跟降低電路布局時間，除了為了減少高延遲電路的硬體面積以及因在數位流程中沒有仲裁電路布局是使用自行電路佈局方式，其他電路以及最後的架構整合均使用數位電路設計流程。本篇論文提出兩種依據解碼吞吐量(throughput)要求找小值電路架構，相較於傳統數位電路實現方式，可以減少約30%的晶片面積以及減少電路延遲。

For low-density parity-check (LDPC) decoders using the min-sum algorithm, the first two minimum values and the first minimum index must be found when updating the check node. Conventionally, this minimum-value finder is implemented digitally using a tree-structure scheme. In this thesis, we propose time-domain minimum-value finders, which process the mixed analog and digital signals. In addition, we propose digital to time converter (DTC) that firstly computes the signal of the most significant bit (MSB) in order to reduce the area of the delay elements. Compared to the conventional tree-structure-based scheme, the proposed time-domain minimum-value finders can reduce chip area and latency by more than 30\%.

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