低光強度條件下影像感測器的敏感度優化設計：0.18µm 標準CMOS製程的實現與分析

簡易檢索 / 詳目顯示

回結果列表

研究生：	許博奕 Hsu, Po-Yi
論文名稱：	低光強度條件下影像感測器的敏感度優化設計：0.18µm 標準CMOS製程的實現與分析 Sensitivity Optimization Design of Image Sensors under Low Light Intensity Conditions: Implementation and Analysis in 0.18µm Standard CMOS Process
指導教授：	徐永珍 Hsu, Yung-Jane
口試委員:	賴宇紳 Lai, Yu-Sheng 黃吉成 Huang, Ji-Chang
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering
論文出版年：	2025
畢業學年度：	113
語文別：	中文
論文頁數：	80
中文關鍵詞：	影像感測器、無基板效應P型源極隨耦器、相關二次取樣、行放大器、標準CMOS製程、N+/pwell光二極體
外文關鍵詞：	CMOS image sensor, PMOS source follower, Correlated double sampling, Column amplifier, Standard CMOS process, N+/pwell Photodiode
相關次數：	點閱：3 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

本研究利用改良式4T-APS CMOS影像感測電路，在TSMC 1P6M 0.18μm標準製程下整合N+/P-well光二極體、像素讀取電路、行放大電路、相關二次取樣電路以及時序控制電路，目標為了達到30 frame/s及解析度Full HD 1920×1080，並提高在影像感測電路在低光環境下之敏感度。
也因為先前缺乏此光二極體之量測數據因此本研究下線之晶片內有額外放置一顆大尺寸之N+/P-well光二極體，為N+/P-well光二極體在逆向偏壓之下之光電特性提供量測數據，以利未來需要之前模擬數據使用。
主要電路輸出之量測結果對於光響應之輸出曲線在線性回歸後，決定係數為0.99911(R^2)，線性相依程度很高，也就代表電路輸出得以直接反應光強度大小。而低光強度之量測表現上，最低得以分辨到55.67lux以上之光強度，雖不符合預期，但對於整體來說是能成功操作之影像感測電路，且為在標準製程下提高低光強度之敏感度有潛力之架構。

This study utilizes an improved 4T-APS CMOS image sensing circuit, integrating an N+/P-well photodiode, pixel readout circuit, row amplifier, correlated double sampling (CDS) circuit, and timing control circuit, fabricated using TSMC standard 1P6M 0.18μm CMOS process. The design aims to achieve a frame rate of 30 frames per second with Full HD 1920×1080 resolution, while enhancing the sensitivity of the image sensing circuit under low-light conditions.
Due to the lack of prior measurement data for this type of photodiode, an additional large-area N+/P-well photodiode was included on the fabricated chip to provide measurement data for the photodiode’s photoelectric characteristics under reverse bias, supporting future simulation and modeling needs.
The measurement results of the main circuit’s output show a high degree of linearity in the light response output curve, with a coefficient of determination (R2) of 0.99911 after linear regression. This indicates a strong linear correlation, demonstrating that the circuit output can directly reflect the incident light intensity.
In terms of low-light performance, the circuit is capable of distinguishing light intensities above 55.67 lux. Although this does not fully meet expectations, the image sensing circuit operates successfully overall and demonstrates potential for enhanced sensitivity to low-light conditions within a standard CMOS process.

摘要    i
Abstract    ii
致謝    iii
目錄    iv
圖目錄    vii
表目錄    x
第一章    前言    1
1    近代影像感測器產業的發展    2
2    研究動機    5
3    論文章節架構    7
第二章    CMOS影像感測器簡介    8
1    CMOS影像感測器的基本架構    8
2    常用的光感測元件    9
3    光感測元件的操作模式    12
4    CMOS影像感測器常見的像素架構    14
4.1    被動式像素感測(Passive Pixel Sensors, PPS)    14
4.2    主動式像素感測(Active Pixel Sensors, APS)    14
4.3    數位式像素感測(Digital Pixel Sensor, DPS)    17
5    衡量CMOS影像感測器表現之參數    17
第三章    低光強度下影像感測器的發展    19
1    減少輸出雜訊以提高敏感度的方式    19
1.1    埋層通道源極隨耦器(Buried Channel Source Follower, BSF)    20
1.2    薄氧化物PMOS源極隨耦器(Thin Oxide PMOS Source Follower)     21
1.3    相關多重取樣(Correlated Multiple Sampling, CMS)    23
2    提高轉換增益來優化在低光下之敏感度    24
2.1    接近單位增益之源極隨耦器(Nearly Unity-Gain Source Follower)     24
2.2  共源極PMOS像素放大器(Common Source PMOS Amplifier)    26
2.3    高讀取行增益(High Gain of Column Level)    27
第四章    測試晶片架構與設計    28
1    感光元件模擬    28
1.1    使用Silvaco進行元件模擬    28
1.2    光二極體SPICE Model    31
2    提高低光強度敏感度之電路架構    32
2.1    像素內電路    32
2.2    行放大電路    35
2.3    相關二次取樣電路(Correlated Double Sampling)    37
2.4    輸出緩衝器    38
3    時序產生電路    40
第五章    測試晶片之模擬與佈局    42
1    測試電路之前模擬結果    44
1.1    像素內電路    44
1.2    在不同光電流下之最終輸出    45
1.3    製程及溫度變異對感測電路設計之影響    48
1.4    電壓變異對感測電路設計之影響    49
1.5    數位電路之模擬結果    50
2    測試電路之佈局    52
3    後模擬結果與前模擬結果之比較    58
第六章    量測架構與量測結果    60
1    測試晶片使用之印刷電路板設計    60
2    量測儀器介紹    61
3    量測方式    63
3.1    時序產生電路量測    63
3.2    偏壓電路量測    63
3.3    主要電路輸出量測    63
4    量測結果分析與討論    65
4.1    時序產生電路    65
4.2    偏壓電路    66
4.3    主要電路輸出    67
4.4    未照光時之雜訊表現    68
4.5    低光強度之下輸出    69
4.6    測試元件在弱光時之光電特性    70
4.7    量測結果討論    71
4.8    本研究中使用之感測電路效能比較    73
第七章    結論與後續研究建議    74
1    結論    74
2    後續研究建議    75
2.1    電路優化以及佈局之改善    75
2.2    開關效應之考量    76
2.3    光感測元件之選擇    76
2.4    電晶體雙重保護環(Double Guard Ring)的使用    77
2.5    測試電路之選擇    77
第八章    參考資料    78

                                

[1] Yole Development. (2024). Status of the CMOS Image Sensor Industry 2024 report sample [Online]. Available: https://www.yolegroup.com/product/report/ status-of-the-cmos-image-sensor-industry-2024/
[2] A. El Gamal and H. Eltoukhy, "CMOS image sensors," in IEEE Circuits and Devices Magazine, vol. 21, no. 3, pp. 6-20, May-June 2005
[3] 雷良煥, 黃吉成, 徐永珍, “後來居上的CMOS 影像感測器,” 物理雙月刊32卷1期, 2010
[4] S. Guissi. (2017). CMOS Image Sensors (CIS): Past, Present & Future [Online]. Available: https://www.coventor.com/blog/cmos-image-sensors-cis-past-present-future/
[5] Canon News. (2019). Future Canon sensor technology - an overview [Online]. Available: https://www.canonnews.com/future-canon-sensor-technology-an-overview
[6] iSUPPLi; IDC; strategies unlimited; JPMorgan; Micron Marking, 2005
[7] M. Sakakibara et al., "A high-sensitivity CMOS image sensor with gain-adaptive column amplifiers," in IEEE Journal of Solid-State Circuits, vol. 40, no. 5, pp. 1147-1156, May 2005
[8] Bigas, M., Cabruja, E., Forest, J., & Salvi, J. (2006). Review of CMOS image sensors. Microelectronics journal, 37(5), 433-451.
[9] PVEducation. Optical Properties of Silicon. [Online]. Available: https://www.pveducation.org/pvcdrom/materials/optical-properties-of-silicon
[10] J. Ohta, Smart CMOS Image Sensors and Applications, CRC Press, 2007
[11] 葉奕良。「光伏模式 CMOS影像感測器之動態範圍擴展」。碩士論文，國立清華大學電子工程研究所，2021。
[12] S. Kleinfelder, SukHwan Lim, Xinqiao Liu and A. El Gamal, "A 10000 frames/s CMOS digital pixel sensor," in IEEE Journal of Solid-State Circuits, vol. 36, no. 12, pp. 2049-2059, Dec. 2001
[13] I. Brouk, A. Nemirovsky, Y. Nemirovsky, "Analysis of noise in CMOS image sensor," in IEEE International Conference on Microwaves, Communications, Antennas and Electronic Systems, 2008, pp.1-8
[14] Behzad Razavi, “Design of Analog CMOS Integrated Circuit”, McGraw-Hill, 2001.
[15] Y. Chen, X. Wang, A. J. Mierop and A. J. P. Theuwissen, "A CMOS Image Sensor With In-Pixel Buried-Channel Source Follower and Optimized Row Selector," in IEEE Transactions on Electron Devices, vol. 56, no. 11, pp. 2390-2397, Nov. 2009
[16] Y. Chen, Y. Xu, Y. Chae, A. Mierop, X. Wang, and A. Theuwissen, “A 0.7e-rms-temporal-readout-noise CMOS image sensor for low-light-level imaging,” in IEEE International Solid-State Circuits Conference, Feb. 2012, pp. 384-386
[17] Y. Chen, J. Tan, X. Wang, A. J. Mierop, and A. J. P. Theuwissen, “In-pixel buried-channel source follower in CMOS image sensors exposed to X-ray radiation,” in Proceedings of IEEE Sensors, Nov. 1-4 2010, pp. 1649-1652
[18] A. Boukhayma, A. Peizerat, and C. Enz, “Temporal Readout Noise Analysis and Reduction Techniques for Low-Light CMOS Image Sensors,” IEEE Transactions on Electron Devices, vol. 63, no. 1, pp. 72-78, Jan. 2016.
[19] C. Lotto, P. Seitz, and T. Baechler, “A sub-electron readout noise CMOS image sensor with pixel-level open-loop voltage amplification,” in 2011 IEEE International Solid-State Circuits Conference, Feb. 2011, pp. 402-404
[20] N. Kawai and S. Kawahito, “Noise analysis of high-gain, low-noise column readout circuits for CMOS image sensors,” IEEE Transactions on Electron Devices, vol. 51, no. 2, pp. 185-194, Feb. 2004
[21] S. Suh, S. Itoh, S. Aoyama, and S. Kawahito, “Column-parallel correlated multiple sampling circuits for CMOS image sensors and their noise reduction effects,” Sensors, vol. 10, no. 10, pp. 9139-9154, 2010
[22] Ge, Xiaoliang, and Albert Theuwissen. "A CMOS image sensor with nearly unity-gain source follower and optimized column amplifier." in IEEE SENSORS, pp. 1-3, 2016.
[23] A. Boukhayma, A. Peizerat and C. Enz, "A Sub-0.5 Electron Read Noise VGA Image Sensor in a Standard CMOS Process," in IEEE Journal of Solid-State Circuits, vol. 51, no. 9, pp. 2180-2191, Sept. 2016
[24] 林祐玄, “標準製程下實現高響應度橫向光感測電晶體之研究", 國立清華大學, 電子工程研究所, 碩士論文, 中華民國一百零六年十月
[25] Analog layout – Wells, Taps, and Guard rings, https://pulsic.com/analog-layout-wells-taps-and-guard-rings/
[26] X. Ge and A. J. P. Theuwissen, "A 0.5erms− Temporal Noise CMOS Image Sensor With Gm-Cell-Based Pixel and Period-Controlled Variable Conversion Gain," in IEEE Transactions on Electron Devices, vol. 64, no. 12, pp. 5019-5026, Dec. 2017
[27] C. T. Tai, M. D. Ker, “Optimization of Guard Ring Structures to Improve Latchup Immunity in an 18 V DDDMOS Process,” IEEE Transactions on Electron Devices, vol. 63, no. 6, pp. 1-6, June. 2016.
[28] “CMOS光電轉換特性”, https://www.cnblogs.com/uestc-mm/p/17493625.html

簡易檢索 / 詳目顯示

相關論文