研究生: |
陳勝瑋 Sheng-Wei Chen |
---|---|
論文名稱: |
適用於無線感測網路的Modified AES的電路實現 An Implementation of Modified AES for Wireless Sensor Network |
指導教授: |
許雅三
Yarsun Hsu |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
論文出版年: | 2005 |
畢業學年度: | 93 |
語文別: | 英文 |
論文頁數: | 98 |
中文關鍵詞: | 無線感測網路 、加解密 、晶片 |
外文關鍵詞: | Wireless Sensor Network, encryption, decryption, chip |
相關次數: | 點閱:2 下載:0 |
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隨著有線、無線通訊的發展,安全性的考量變的越來越重要。如果沒有可靠的安全機制,許多應用將受到很大的限制,諸如:電子商務,網路銀行。
先進加密標準 (Advanced Encryption Standard) 演算法是一種新型的對稱式加密系統,它是美國的國家標準及工業技術學會 (National Institute of Standards and Technology) 為了取代已經使用了超過三十年的資料加密標準(Data Encryption Standard) 所推動的一個新的密碼標準。近兩年來,有許多實現AES演算法的硬體已經被發表,但在這些電路的設計中,通常使用唯讀記憶體或隨機存取記憶體 (ROM 或 RAM) 來實現AES 演算法中一關鍵的構成要件 S-box,這種方式的好處是在硬體的實現上相當的方便,可以將所需要的結果直接使用查表的方式求得,但缺點是這種方式將會耗費較多的晶片面積。另外,有別於事先運算金鑰產生程序的方法,我們利用即時金鑰產生程序的方法來產生回合金鑰。這種即時金鑰產生程序的好處在於它可降低功率的消耗。
無線感測網路常被使用於軍事用途上,像是收集敵人的資訊。因此節點之間資料傳送的保護就非常重要。所以在資訊傳送之前對資訊進行加密是必要的。
我們實現了一個適用於無線感測網路節點的加解密晶片。由於無線感測節點上的資源跟電源供應通常是受限制的,所以這個電路最重要的課題在於功率消耗跟邏輯閘數。我們以AES為基礎,創造出modified AES演算法。
我們把SubBytes跟MixColumns中的乘法利用三個不同的表結合起來以減少邏輯閘數。此外,因為InvSubBytes和SubWord 的GF(24)2 inverter是共用的,所以我們利用composite field的計算方式來實現以達到較少的邏輯閘數。我們的電路總共大約有45,500個邏輯閘。
由於modified AES功率消耗最嚴重的部分是S-box和Inverse S-box,所以我們使用三級的AND-XOR架構來設計S-box和Inverse S-box以降低功率消耗。我們電路的功率消耗大約是42.53毫瓦。
Wireless sensor networks are usually used in military applications, such as gathering enemies’ information. Therefore, the protection of data transfers between nodes from enemies is critical. It is necessary to encrypt the information before the information is transmitted.
We implement an Encryption/Decryption chip that is suitable for applications in wireless sensor network nodes. The most important issues are the power consumption and gate count of the circuit because resources and power supply are usually limited in wireless sensor nodes. We create modified AES algorithm based on AES.
We combine SubBytes () with multiplications of MixColumns () by means of three different tables to reduce gate counts. In addition, we implement InvSubBytes () and SubWord () with composite field calculation because the sharing of GF(24)2 inverter leads to lower gate count. The total gate count of our circuit is about 45.5K.
Besides, since the most power-consuming parts of modified AES are S-box and Inverse S-box we use 3-stage AND-XOR architecture in the designs of S-box and Inverse S-box to get lower power dissipation. The power consumption of our circuit is about 42.53mW.
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