隨著現今超大型積體電路(VLSI)製程尺寸越來越小，也越來越複雜。一個晶片當中所需要的層數也會越來越多，這伴隨而來的問題就是會使得我們晶圓表面凹凸不平的情況會加劇，為了可以配合現今光蝕刻的技術，我們需要一個表面平坦的晶圓。否則可能會導致我們做光蝕刻時造成錯誤。而化學機械平坦化(CMP)是現在製程技術當中最能夠確保晶圓表面平整也最廣泛被使用的一項技術。但為了使CMP可以完美的運作，我們必須確保晶圓表面密度分布的平均，CMP結果的好壞與晶圓表面密度分布平均與否有很大的關聯，所以我們透過使用虛擬金屬填充的方法來使得我們晶圓表面密度分布平均，進而提升IC製程時的良率。我們使用Liner Programming(LP)的方法來得到每個子區塊理想的密度，再透過我們有效率的虛擬金屬填充方法填入虛擬金屬。我們與ICCAD 2014比賽的前三名隊伍有著相當的實驗結果。

As the shrinking of device geometries scale, there is an inevitable need for better planarization of the multilevel interconnect structures. To meet today's advanced lithography methods, we need a planar surface. Or may leads to bad lithography results. CHEMICAL MECHANICAL POLISHING(CMP) is the planarizing technique of
options to generate a good planarity result. But there is one problem for CMP to work perfectly, it can not have large stretches of metal or non-metal regions. Dummy fill has been demonstrated to be an effective technique to fix the planarity issue and to improve the manufacturability for advanced integrated circuit (IC) designs. We propose an liner programming (LP) formulation with some new considerations involved to determine the density of each region and an efficient fill insertion flow. Comparing with the experimental achievement for ICCAD 2014 contest benchmarks, we have a comparable result.

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