在元件日漸微縮的趨勢下，平面式元件微縮空間有限，造成元件密度難增加且製程難度跟著大幅的提升，如何提升電性又能提高元件密度為目前重要的課題之一。有些解決方法已漸漸被提出，如高介電常數材料的應用、奈米線通道的結構、無接面快閃記憶體元件的應用和多晶矽、矽化鍺通道材料的應用等等。鍺相較於矽有比較高的電子遷移率，且多晶鍺元件可以使用低溫製程(<600˚C)，可以降低製程熱預算。多晶鍺材料在未摻雜時為P型半導體，通道摻雜對多晶鍺快閃記憶體影響目前沒有相關研究。本篇論文使用多晶鍺無接面快閃記憶體，對於通道摻雜進行研究，並使用ICPCVD達到低溫製程。
　　在本論文中，第一個實驗是針對不同摻雜的多晶鍺通道無接面快閃記憶體做比較。有摻雜的多晶鍺元件在寫入抹除上都有較好的表現，在電荷保持力及寫抹耐久力也有較好的表現。而在有摻雜的多晶鍺元件中，N型通道的多晶鍺元件在各方面都有較好的表現，因為通道中主要載子為電子，寫入抹除電流較大，通道與介面態位較少。
　　第二個實驗是將低溫沉積氮化矽堆疊電荷捕捉層應用在N型通道多晶鍺快閃記憶體元件上，希望可以改善多晶鍺快閃記憶體的特性。二氧化鉿/氮化矽堆疊電荷捕捉層元件在寫抹速度有較好的表現，氮化矽較高的能障對電荷保持力也有改善，相較於單層氮化矽或是二氧化鉿/氧化鉿鋁電荷捕捉層也有較好的表現。
　　第三個實驗是使用二氧化鉿/氮化矽堆疊電荷捕捉層結構，比較在低溫製程下多晶鍺及多晶矽元件的特性差異。多晶矽元件在寫抹速度表現較好，因為穿隧氧化層較薄，且通道大小較小。N型摻雜通道多晶鍺元件在快閃記憶體表現較好，因為通道中主要載子為電子，寫入抹除電流較大，通道態位較少。在開關電流比及電晶體基本特性上P型摻雜通道多晶鍺元件表現較好，可能是因為P型多晶鍺的通道介面較好。

The scale down of planar flash device is limited by its capability of micro-miniature, which makes the process flow more complex. How to improve the electrical characteristics and increase the device density at the same time becomes two of the most important issues. Some approaches have been reported such as the implement of high-k materials, nanowire channel structure, junctionless channel, poly-Si channel and SiGe buried channel. The carrier mobility of Ge is higher than that of Si. poly-Ge devices can be fabricated at low temperature process (<600˚C), which can reduce process thermal budget. Poly-Ge film is naturally p type without any implantation. There is no report about the effect of channel dopant on poly-Ge. In this thesis, we implement poly-Ge on junctionless channel flash memory devices, and the characteristics of channel dopant are investigated. The low temperature process was achieved by ICPCVD.
In the first experiment, the characteristics of channel dopant on poly-Ge junctionless flash memory are investigated. The results show that doped poly-Ge devices perform better on program/erase speed, retention, and endurance. The poly-Ge device with N type dopant perform better because the main carriers of channel are electrons. The injection current of program/erase is higher and the interface states between channel and tunneling layer are fewer.
In the second experiment, to improve the characteristics of poly-Ge flash memory, low temperature formed Si3N4 is applied to N channel poly-Ge flash memory device. The HfO2/Si3N4 stacked charge trapping layer perform better on program/erase speed. Furthermore, the Si3N4 layer improve retention performance because of high energy barrier.
In the third experiment, the characteristics of poly-Ge and poly-Si devices with low temperature process by using HfO2/Si3N4 stacked charge trapping layer are investigated. The poly-Si device performs better on program/erase speed because of thinner tunneling oxide and smaller channel dimension. The N channel poly-Ge device performs better because the main carriers of channel are electrons. The injection current of program/erase is higher and the interfaces state between channel and tunneling layer are fewer. The P channel poly-Ge performs better on on/off ratio and transistor characteristics because of better channel interface of P channel poly-Ge device.

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