我們利用在相臨管線階段(Pipeline Stages)插入環狀佇列(Cyclic Queue)架構的方式來提昇整個H.264/AVC 主要檔次(Main Profile)解碼器的解碼效能，使其可以達到四倍於高清晰度(4xHD/QFHD)大小影像的即時解碼(每秒至少解三十張)。此外，考慮到加入環狀佇列後對整個解碼器的面積所造成的影響，我們使用遞迴(iterative)的模擬(Simulation)、分析(Analysis)、判斷(Decision)是否增大環狀佇列的大小的方式，來動態決定每一個環狀佇列中單元(entry)的個數，以便在整體解碼效能提昇和其所需額外增加的面積中做出較好的選擇。此方式的好處在於若是今後若是解碼器中某一部分小單元(sub-function)的效能提昇，我們只需在跑一次這個流程便可以得到較佳的解碼效果，而不需再大幅度修改整個解碼器的架構。在整體解碼效能評比方面，若在相同的運作時脈與晶片面積的條件下，相對於我們未使用環狀佇列的解碼器，使用環狀佇列的解碼器至少增加了百分之十四的解碼效能；另外，相對於其他現行的H.264解碼器，採用環狀佇列的解碼器至少提昇了百分之二十七以上的解碼效能。最後，我們的解碼器只需運作在一百四十百萬赫茲(MHz)便可以滿足四倍高清晰度影像的即時解碼的要求，如此高的解碼效能將可實現許多要求大畫面、高解析度的應用(例如：太空探勘、醫學影像、數位監控)。對於未來的研究方向，我們會朝更省電(Lower Power)、更大解析度(Higher Resolution, i.e. 16xHD)及更高解碼效能(Higher Throughput)的解碼器為今後努力的目標。

We propose a cyclic-queue buffering scheme to reduce bubble cycles in the pipeline of a pure hardwired H.264/AVC main profile decoder. After analyzing hardware cost and throughput gain, a moderate number of memory blocks is inserted between stages. Under the same critical path constraint, the decoder gains 14% performance improvement at the expense of 5% area overhead. The proposed design only has to run at 140 MHz when decoding QFHD (4X 1080HD) video sequence at 30 frames per second.

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