現今人們對於網路的依賴性與日俱增，而網路的使用也隨著科技的進步從有線網路轉變成無線網路，而提及無線網路最容易聯想到的就是生活中隨處可見的Wi-Fi，只需要一個小小的收發基地台，就可以盡情的利用網路滿足個人的需求，因此，對於研究積體電路如何應用於Wi-Fi電路系統中，也是為具實用性與挑戰性的研究題材。本論文提出了具2.8–4.8 GHz調變範圍的三角積分調變之鎖相迴路，主要組成電路有相位頻率偵測器、充電幫浦、三階迴路濾波器、多頻帶之壓控震盪器、具三角積分調變器控制之除頻器，利用運算放大器降低充電幫浦之非理想效應，採用切換式電容對提升電容電感式壓控震盪器之操作頻率範圍，十六位元之三角積分調變器達成所需之除數解析度，以上子電路建立出完整的鎖相迴路架構，此外，本論文提出之應用於Wi-Fi系統之鎖相迴路利用晶圓廠之1P7M的55nm製程模擬設計完成後進行晶片下線，本論文提出之鎖相迴路面積消耗為0.32mm2，消耗功率為24mW，理論除數解析度可達1/65536，操作頻率範圍由64個頻帶所劃分而成，相位頻率鎖定時間為1.25μs。內文開頭為介紹各種鎖相迴路架並且加以比較，接著依序講解鎖相迴路之數學模型、設計流程、提出電路架構之模擬結果、下線晶片的量測考量，最後對於提出之鎖相迴路做統合性的結論。

In recent years, people are increasingly more and more dependent on internet. With the advancement of science and technology, the methods of surfing on the internet turn from wire network to wireless network. When it comes to wireless internet in our daily life, people always associate Wi-Fi. The requirements of everyone can be satisfied by using wireless internet and it merely needs a small router AP. Therefore, it is a practical and challenging study subject that the integrated circuits can be applied to the circuit architecture of the Wi-Fi system.
A delta-sigma phase locked loop with 2.8–4.8 GHz tuning range was proposed in this thesis. The main architecture of proposed PLL is divided in several parts, phase and frequency detector, charge pump, 3rd loop filter, multi-band voltage controlled oscillator, and a divider controlled by delta-sigma modulator. The non-ideal effect of charge pump was reduced by adding a unit gain buffer. The wide tuning range of voltage controlled oscillator was mainly due to six pairs of switched capacitors. The high enough resolution of divisor is fulfilled by 16-bit delta-sigma modulator. The entire architecture of proposed PLL was composed by the circuits mentioned above. In addition, the circuit of proposed PLL was fabricated using a 1P7M 55nm standard CMOS technology and the core circuit occupied an area of 0.32 mm2. The experiment results indicated the total power consumption is 24 mW at 1.2 V supply voltage, the theoretical resolution of the divisor is 1/65536, the range of operation frequency was divided in 64 bands, and the locked time was 1.25 μs.
Besides, the comparison of three kinds of PLLs was as the beginning of this thesis, and the mathematical model of PLLs, the designed flow, the simulation results of proposed circuits, the considerations of measurement were described step by step. Finally, an integrated conclusion for the proposed PLL was given in the last chapter.

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