運用群體熱感知及共生系統架構提高基於憶阻器的脈衝神經網路硬體可靠度

簡易檢索 / 詳目顯示

回結果列表

研究生：	高愷德 Kao, Kai-Te.
論文名稱：	運用群體熱感知及共生系統架構提高基於憶阻器的脈衝神經網路硬體可靠度 A Thermal Quorum Sensing Scheme and Symbiotic Neuromorphic Architecture for Highly Reliable Memristor-Based SNN Hardware
指導教授：	吳誠文 Wu, Cheng-Wen
口試委員:	劉靖家 Liou, Jing-Jia 黃錫瑜 Huang, Shi-Yu 呂學坤 Lu, Shyue-Kung
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2023
畢業學年度：	111
語文別：	英文
論文頁數：	43
中文關鍵詞：	人工智慧加速器、電路補償、容錯性、脈衝神經網路、共生系統、憶阻器的脈衝神經網路
外文關鍵詞：	AI accelerator, circuit compensation, error tolerance, spiking neural network, symbiotic system, memristor-based neural network
相關次數：	點閱：1 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

由於電晶體數目的指數增長趨勢，超大型積體電路的複雜程度不斷提高，許多微小的製程缺陷難以透過傳統的測試方法進行檢測。然而這些微小的缺陷可能會降低晶片產品的品質與可靠性。在本論文中，基於一個以憶阻器建構的脈衝神經網路架構，我們的實驗展示了在高密度電阻式記憶體單元陣列中的微小硬體缺陷，可能導致晶片的計算準確度下降，也可能因為功率消耗上升，在晶片內部產生額外的熱源。為了提升晶片的可靠度，我們提出運用群體熱感知及共生系統架構以提升基於憶阻器的脈衝神經網路硬體的可靠度。我們也提出了一個低功耗與低成本的溫度感測器電路架構，可以被大量部署於群體熱感知系統中，以偵測晶片中的熱源分布佈情形。我們也提出了共生系統架構，透過一個次系統脈衝神經網路，我們對熱源分佈情形進行監控，以推論主系統脈衝神經網路中是否存在錯誤。實驗結果顯示，次系統脈衝神經網路進行偵錯的準確度可達到91.6%，整個群體熱感知及共生系統僅增加2.48%晶片面積。當有錯誤被偵測到時，藉由調整脈衝神經網路中神經元的閾值電壓進行補償，我們可以減緩晶片計算結果的準確度下降趨勢，進而提升晶片的可靠度。

Due to the exponential growth of transistor density and complexity of VLSI circuits, it is increasingly challenging to detect the subtle defects in VLSI circuits by traditional testing methods. These hard-to-detect defects, however, may degrade the product’s reliability and quality. In this paper, based on a memristor-based spiking neural network (SNN) architecture that we have designed, we show that the subtle defects in the compact memristor cell array and the SNN functional faults may result in inference accuracy loss and extra heat generated by the SNN chip. To achieve a reliable memristor-based SNN chip, we propose an on-chip thermal quorum sensing scheme that can monitor the temperature distribution on the chip. We also propose the symbiotic neuromorphic architecture, where a secondary-SNN is developed for on-line real-time failure detection for the primarySNN. Simulation results show that the secondary-SNN achieves 91.6% detection accuracy, with only 2.48% silicon area overhead. When a failure is detected, our compensation scheme can recover the inference accuracy loss of the SNN chip.

Abstract (Chinese) . . . . . . . . . . . . . . . . . . . . . . . I
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . II
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . III
List of Figures . . . . . . . . . . . . . . . . . . . . . . . .  V
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . VIII
Introduction . . . . . . . . . . . . . . . . . . . . . . . . .  1
1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . .  1
2 Proposed Method and Results . . . . . . . . . . . . . . . . . 2
3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . 3
Background . . . . . . . . . . . . . . . . . . . . . . . . . .  4
1 Introduction to Symbiotic System . . . . . . . . . . . . . .  4
2 Introduction to Thermal Quorum Sensing . . . . . . . . . . .  5
2.1 Quorum Sensing . . . . . . . . . . . . . . . . . . . . . .  5
2.2 Introduction to Thermal Quorum Sensing . . . . . . . . . .  5
3 Introduction to Spiking Neural Network . . . . . . . . . . .  6
4 Introduction to Memristor-Based SNN . . . . . . . . . . . . . 7
4.1 Memristor . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 1T1R Memristor Structure . . . . . . . . . . . . . . . . .  8
4.3 Memristor-Based SNN Chip . . . . . . . . . . . . . . . . .  9
Proposed Thermal Sensor Circuit . . . . . . . . . . . . . . . . 14
1 Circuit Schematic and Layout . . . . . . . . . . . . . . . .  15
2 Sensor Design Concept . . . . . . . . . . . . . . . . . . . . 16
3 Circuit Calibration Methodology . . . . . . . . . . . . . . . 20
Online Monitoring System . . . . . . . . . . . . . . . . . . .  24
1 Memristor Power Model . . . . . . . . . . . . . . . . . . . . 24
2 Memristor-Based SNN Faulty Behavior . . . . . . . . . . . . . 26
3 Thermal Quorum Sensing Scheme . . . . . . . . . . . . . . . . 28
3.1 Thermal Quorum Sensing Scheme . . . . . . . . . . . . . . . 28
3.2 Secondary Neural Network . . . . . . . . . . . . . . . . .  29
4 Compensation Technique . . . . . . . . . . . . . . . . . . .  30
Experimental Results . . . . . . . . . . . . . . . . . . . . .  32
1 Fault-Free Power & Temperature . . . . . . . . . . . . . . .  33
2 Faulty Power & Temperature . . . . . . . . . . . . . . . . .  34
3 Secondary Neural Network Testing Result . . . . . . . . . . . 36
4 Area Overhead . . . . . . . . . . . . . . . . . . . . . . . . 37
5 Compensation Results . . . . . . . . . . . . . . . . . . . .  37
Conclusion and Future Work . . . . . . . . . . . . . . . . . .  39
1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . .  39
2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . 40
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . .  41
                                

1. L.-T. Wang, C.-W. Wu, and X. Wen, VLSI Test Principles and Architectures: Design for Testability. Elsevier, 2006.
2. H. Qi, S. Ganesan, and M. Pecht, “No-Fault-Found and Intermittent Failures in Electronic Products,” Microelectronics Reliability, vol. 48, pp. 663–674, May. 2008.
3. R. Rajsuman, “IDDQ Testing for CMOS VLSI,” Proceedings of the IEEE, vol. 88, pp. 544–568, Apr. 2000.
4. M. S. Floyd, S. Ghiasi, T. W. Keller, K. Rajamani, F. Rawson, J. C. Rubio, and M. S. Ware, “System Power Management Support in the IBM POWER6 Microprocessor,” IBM Jour. of Research and Development, vol. 51, pp. 733–746, Nov. 2007.
5. P.-Y. Chuang, C.-W. Wu, and H. H. Chen, “Covering Hard-to-Detect Defects by Thermal Quorum Sensing,” in Proc. 2018 IEEE 23rd European Test Symp. (ETS), pp. 1–2, May. 2018.
6. H.-H. Wang, P.-Y. Chuang, and C.-W. Wu, “A Thermal Quorum Sensing Scheme for Enhancement of Integrated-Circuit Reliability and Lifetime,” in Proc. 2022 Int. Symp. VLSI Design, Automation and Test (VLSI-DAT), pp. 1–4, Apr. 2022.
7. B. Yan, Q. Yang, W.-H. Chen, K.-T. Chang, J.-W. Su, C.-H. Hsu, S.-H. Li, H.-Y. Lee, S.-S. Sheu, M.-S. Ho, et al., “RRAM-Based Spiking Nonvolatile Computing-in-Memory Processing Engine with Precision-Configurable in situ Nonlinear Activation,” in Proc. 2019 Symp. VLSI Technology, pp. T86–T87, June. 2019.
8. K.-W. Hou, H.-H. Cheng, C. Tung, C.-W. Wu, and J.-M. Lu, “Fault Modeling and Testing of Memristor-Based Spiking Neural Networks,” in Proc. IEEE Int. Test Conf. (ITC), Sept. 2022.
9. C.-W. Wu, “Symbiotic-System Approach for IOT devices,” in Proc. 25th IEEE Asian Test Symp.(ATS), Nov. 2016.
10. C.-W. Wu, B.-Y. Lin, H.-W. Hung, S.-M. Tseng, and C. Chen, “Symbiotic System Models for Efficient IOT System Design and Test,” in Proc. 2017 Int. Test Conf. in Asia (ITC-Asia), pp. 71–76, Sept. 2017.
11. B.-Y. Lin, H.-W. Hung, S.-M. Tseng, C. Chen, and C.-W. Wu, “Highly Reliable and Low-Cost Symbiotic IOT Devices and Systems,” in Proc. 2017 IEEE Int. Test Conf. (ITC), pp. 1–10, Oct. 2017.
12. M. B. Miller, B. L. Bassler, et al., “Quorum Sensing in Bacteria,” Annual Review of Microbiology, vol. 55, pp. 165–199, Oct. 2001.
13. K. L. Visick and C. Fuqua, “Decoding Microbial Chatter: Cell-Cell Communication in Bacteria,” Jour. of Bacteriology, vol. 187, pp. 5507–5519, Aug. 2005.
14. G. K. Johnsen, “An Introduction to the Memristor-A Valuable Circuit Element in Bioelectricity and Bioimpedance,” Jour. of Electrical Bioimpedance, vol. 3, pp. 20–28, Jan. 2012.
15. C. Zamarre˜no-Ramos, L. A. Camu˜nas-Mesa, J. A. P´erez-Carrasco, T. Masquelier, T. Serrano-Gotarredona, and B. Linares-Barranco, “On Spike-TimingDependent-Plasticity, Memristive Devices, and Building a Self-Learning Visual Cortex,” Frontiers in Neuroscience, vol. 5, p. 26, Mar. 2011.
16. T. Serrano-Gotarredona, T. Masquelier, T. Prodromakis, G. Indiveri, and B. Linares-Barranco, “STDP and STDP Variations with Memristors for Spiking Neuromorphic Learning Systems,” Frontiers in Neuroscience, vol. 7, p. 2, Feb. 2013.
17. H. Liu, H. Lv, B. Yang, X. Xu, R. Liu, Q. Liu, S. Long, and M. Liu, “Uniformity Improvement in 1T1R RRAM with Gate Voltage Ramp Programming,” IEEE Electron Device Letters, vol. 35, pp. 1224–1226, Dec. 2014.
18. K.-W. Hou, A Power-Efficient Memristor-Based Spiking Neural Network for Real-Time Object Classification. PhD dissertation, Dept. Electrical Engineering, National Tsing Hua Univ., Hsinchu, Taiwan. (in preparation).
19. S. Sze and K. Ng, “Chapter 3 Metal-Semiconductors Contacts,” Physics of Semiconductor Devices, 3rd ed.; John Wiley & Sons: Hoboken NJ, USA, pp. 134–196, 2007.
20. J. Tzou, C. Yao, R. Cheung, and H. Chan, “The Temperature Dependence of Threshold Voltages in Submicrometer CMOS,” IEEE Electron Device Letters, vol. 6, pp. 250–252, May 1985.
21. W. Huang, S. Ghosh, S. Velusamy, K. Sankaranarayanan, K. Skadron, and M. R. Stan, “HotSpot: A Compact Thermal Modeling Methodology for EarlyStage VLSI Design,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 14, pp. 501–513, May 2006.

簡易檢索 / 詳目顯示

相關論文