現今因為系統晶片設計的複雜度不斷的快速增加，在晶片系
統建構初期，電子系統層級模型可以快速的評估效能與成本來縮短
設計的週期。對於整個晶片系統來說，記憶體系統扮演了一個很重
要的角色，不但影響了整個效能，也影響了整個系統的功率
　　然而，對於已存在的一些記憶體模擬器(DRAMSim2)來說，
都只是單純的C++模型，在電子系統層級上的時間並不是準確
的，而且設計來說都只有支援單端口的記憶體，但多端口的記憶
體現今越來越成為主流，在我們的電子系統層級記憶體模型中，
不只支援多端口的架構，也實作一些記憶體指令排序的方法，再
經過RTL的驗證，記憶體模型的時間準確度高達95%，而且速度高
達700k/cycle。
對於記憶體系統的功率，我們也有相對應的模型來支援。記憶體
系統的功率分成三部分，記憶體控制器、記憶體設備、埠物理層三
個部分。每個功率狀態與平均功率都可以分別計算出來，根據簡化
過後的記憶體功率有限狀態機，就可以估算大部分的功率值。
　　整個結果經過電子系統模型的參數優化後，可以得到比原本
好10%的效能。另外經過記憶體控制器的架構延伸，也可以得到比
原本好10%的效能，最後也可以藉由這個模型來探討整個系統對於
記憶體效能與成本的平衡。

Nowadays the complexity for system chip design is rapidly increasing. In order to
reduce the design period, ESL model can be the solution for evaluating during the
early system construction. For full system, memory system plays an important role,
and it is often considered to be a bottleneck, even affect the performance. Because
memory has great influence not only in the performance, but also in the power. We
need to develop an ESL memory system model for evaluating the system.
For the existing memory system design(DRAMSim2) which is a pure C++
model, the timing it calculates is not accurate. DRAMSim2 only supports one port
scheduling policy, but multi-ports memory system design seems to be the mainstream.
In our memory model, we support multi-ports memory system design, and
some commercial command reordering policies. After verification with RTL memory
system, our ESL memory model’s timing accuracy is up to 95%. Its simulation
speed is up to 700k cycle/s.
For memory system power, we also support power modeling. We divide memory
system power into three parts. They are memory controller power, PHY layer power,
memory device power. Each power consumption can be estimated individually, and
total power consumption is calculated. According to the simplified memory finite
state machine, we can estimate most of power consumption. The simulation result
shows the power is very close with data sheet. For memory controller power and
PHY power, we can obtain its value from cooperation company. These information
can be used for evaluating and analyzing the full system design.
The result shows the performance will be 10% better after optimized memory
controller parameters. We can also do the architecture exploration. After analysis,
we obtain 10% better after exploration. On the other hand, we can discuss the
trade-off between performance and buffer area to find a balance.

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