With the growth of the IT industry, the technologies for communication applications attract more and more attention in these years. Recently, the demand for high data rate makes the research of RFICs moving toward higher frequencies with an extended bandwidth. In this study, we use mainly two techniques for wideband amplifier design, balanced amplifier and distributed amplifier. We focus on how to improve the issues existing in conventional configurations, and also try to increase the bandwidth of the amplifiers with the minimum extra power consumption.
First, we design two balanced amplifiers in 0.18 □m TSMC standard CMOS technology. The design of couplers is critical in balanced amplifier, in which the Lange coupler is adopted with the proposed pattern ground shield technology. The noise cancelling technique and dual-gate MOSFETs are employed for the active circuits. Form the result of measurement, these technologies can not only improve the noise but also increase the bandwidth of the balanced amplifiers.
Second, we design the distributed amplifiers with the proposed gate-drain coupling feedback approach to reduce the power consumption and increase the bandwidth simultaneously. The folded topology is used to achieve a compact layout and reduce the loss of the metal stubs. This structure is produced in 0.18□m and 90nm TSMC stand CMOS technology. This structure is further improved by cascading two gain stages to reduce the supply voltage of circuit for low power consumption. From the measurement results, the gate-drain coupling feedback can effectively increase the bandwidth and reduce the power consumption of the distributed amplifiers.

隨著資訊科技的發展，近年來人們對於通訊技術的需求愈顯重要。由於對高速率傳輸的需求增加，使得射頻晶片的設計開始不斷的向高頻以及寬頻進行研究。本研究針對常見的兩種寬頻放大器；平衡式放大器以及分散式放大器進行研究以及設計，分別針對放大器的缺點進行改善並同時提升寬頻放大器的增益頻寬。
首先文中先針對平衡式放大器進行設計，在0.18微米台積電標準CMOS製程上設計了兩種架構，偶合器的部分；皆使用藍基耦合器為基底，搭配pattern ground shield技術進行設計。而放大器部份分別是利用雜訊抵銷技術以及實驗室研究之疊接形式的雙閘極金氧半場效電晶體模型進行設計，後者並搭配寬頻提升技術已達到耦合器所及之最寬的頻寬。經由量測結果可知，以上技術確實能減少平衡式放大器的雜訊以及寬頻提升技術對放大器頻寬的提昇。
其後針對分散式放大器進行設計，利用閘極-汲極電感回授技術進行設計，以減少功率損耗並提升增益頻寬，並且將電路佈局做了凹折設計，已達到較小的面積以及較低的金屬走線損失。此架構分別利用0.18微米以及90奈米台積電標準CMOS製程上設計。最後，將此架構進行進一步的改善，利用串接方式進行分散式放大器的設計，以節省電路所需要的供應電壓。經由量測結果可知，閘極-汲極電感回授技術能提升放大器的頻寬，並減少電路的功率損耗。

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