本論文主要探討應用於無線通訊之可調式低複雜度及低功率消耗多重輸入多重輸出 (MIMO) 偵測器的矽智財 (IP) 設計，其內容包含先前相關研究的研讀，系統模擬與架構設計，以及電路設計和晶片實現。

許多關於MIMO研究包括線性與非線性的偵測方法已經被討論過，基於這些經過充分研究的偵測方法，本論文提出了一個具有低複雜度及高效能的可調式MIMO偵測器架構。其中，低複雜度來自於將MIMO偵測器分成兩個部分：核心部分與剩餘部分，接著一般著名的偵測方法如排序連續干擾消除 (OSIC) 可以被應用到此兩具有較小維度的部分以降低複雜度；另一方面，為了增加偵測效能，本論文提出一個簡化後的最大相似解法 (Simplified MLD) 應用在核心部分；再者，藉由分割MIMO偵測器後所得之基本模組，可用以建立不同天線組態的偵測器，實現可調式的架構。

本論文中，系統模擬建立在MIMO衰減通道矩陣及高斯雜訊模型上，通道矩陣中各元素假設為個別獨立分布，此分布為平均值為0，變異數為0.5之複數高斯分布，通道之頻率響應假設為平坦衰減且為半準靜通道。

為了簡化電路面積與功率消耗，經過分析後一些硬體的簡化被使用，電路採用暫存器交換層級語言描述 (RTL) ，並經由cell-based的積體電路設計流程完成設計，最後使用台積電0.13 um (TSMC 0.13 um) 技術製作晶片。本MIMO偵測器電路的最高操作頻率為62.5 MHz，在最高操作頻率及1.2 V的操作電壓下，預估的功率消耗約為50 mW；可支援的傳送天線數目為2到4，接收天線數目為4到6，並且支援4種不同調變方式，最高為64-QAM。

在晶片製作後，一些增強的電路功能也被提出，包含了進階的降低功率消耗技巧以及電路吞吐量的增加，這些技術提供了在未來實現一個更優秀MIMO偵測器的契機。

In this thesis, specification study, system simulation, architecture design and circuit design along with chip implementation of a low complexity and low power MIMO detector for wireless communications with scalability is presented.

Several types of MIMO systems for wireless communication are
discussed and the related receiving techniques such as linear and non-linear detection methods are also introduced. Based on these well-studied detection methods, a scalable MIMO detector architecture with low complexity and high performance is proposed.
The proposed architecture is low complexity by dividing a large MIMO detector into two parts called core part and residual part, and then the general detection method such as Ordered Successive Interference Cancelation (OSIC) can be applied in each part with smaller dimension. To enhance the detection performance, a Simplified Maximum Likelihood (SML) is also proposed in the core part. Moreover, the proposed architecture is easily scalable because the
detector is divided into several basic building blocks.

Simulations are based on the MIMO fading channel model with white noise. The elements in the channel matrix are assumed i.i.d. complex Gaussian random variable with zero mean and variance of 0.5 per dimension. Simulations are under flat fading and quasi-stationary environment.

To minimum the area and power of the proposed MIMO detector, some hardware simplifications are applied after cost analysis. The proposed detector is implemented with the synthesizable RTL by cell-based ASIC design flow. The detector chip is fabricated with a TSMC 0.13 um 1P8M technology. The maximum operational clock rate is simulated at 62.5 MHz. Power consumption is 50 mW at 1.2 V supply voltage under the maximum clock rate. The chip can
support two up to four transmitted streams and two up to six
received streams with BPSK, QPSK, 16-QAM and 64-QAM modulation types.

After fabrication the IC, several enhancements are also proposed such as advanced low power technique and throughput enhancement. These provide a chance to implement an excellent MIMO detector chip in the future.

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