The Pi-gate nanowires (NWs) and the HfO2 trapping layer were introduced to the polycrystalline silicon (poly-Si) thin film transistor (TFT) nonvolatile memory (NVM). In the recent years, low-temperature poly-Si TFTs have drawn much attention because of their wide applications on active matrix crystal displays (AMLCDs), and organic light-emitting diodes (OLEDs). Furthermore, the low-temperature poly-Si TFTs will help to carry out three-dimensional integrated circuits (3D-ICs) or multilayer Si ICs for system-on–chip (SOC) and fully functional system-on-panel (SOP) applications.
A silicon nitride film is widely used as the charge trapping layer in a nonovolatile memory, and this memory is called silicon-oxide-nitride-oxide-silicon (SONOS) memory. The fabrication of SONOS is simple and the Si3N4 film has spatial isolated traps and robustness to the defect related leakage. All these advantages, as mentioned above, are good for device scaling. In this thesis, the HfO2 film is used for better memory reliability due to the deeper conduction band.
Multi-gate TFTs exhibit low leakage current in the off state, a high ON/OFF current ratio, a low subthreshold slope, an absence of DIBL, and favorable output characteristics. [1-10] Moreover, the multi-gate TFTs have higher program and erase speed due to the high vertical electric field at each corner.
In this thesis, we compared the program and erase speeds of the TFT memories with NWs and single-channel (SC). Obviously, the NWs TFT memories show much higher performance. We also focused on the reliability to the memory applications. The experimental results showed that the Pi-gate NWs poly-Si TFT memories are suitable for the real applications.

此篇論文的研究主題為具氧化鉿電荷儲存層與π形狀閘極之奈米線結構低溫複晶矽薄膜電晶體記憶體，主要應用於平面顯示器上與3D堆疊結構的非揮發性記憶體，論文中利用多晶矽為主動層以降低串聯電阻；使用氧化鉿為缺陷層以增加記憶體的可靠度；多條Pi形狀之奈米線結構以提升寫入以及抹除資料的效率，在論文列出的各項數據顯示出具氧化鉿缺陷層與π形狀閘極之多條奈米線結構低溫複晶矽薄膜電晶體非揮發性記憶體為一高效能記憶體且適合應用於系統整合之平面顯示器。
相較於非晶矽薄膜電晶體，低溫複晶矽薄膜電晶體其主動層擁有十分高的載子遷移率，此項優點有利於電晶體尺寸的微縮以及增加電晶體的操作速度，進而有效提高積體電路元件的密度與增加晶片的功能與設計彈性，因此平面顯示器的系統整合之路邁開了一大步。氮化矽常被應用於浮停閘結構的記憶體中，使用此材料的記憶體比起傳統的多晶矽電荷儲存層更有微縮的潛力，由於氧化鉿與氧化矽的傳導帶差值大於氮化矽與氧化矽的傳導帶差值，因此論文中使用了氧化鉿取代氮化矽為缺陷層的材料，以進一步增加記憶體的可靠度。在先前的研究已經證實π形狀之多條奈米線閘極結構能提高多晶矽薄膜電晶體的電晶體特性[1-10]，靠著其優異的閘級控制能力，亦能加速資料的寫入以及抹除，在論文的實驗數據中，證明了此特性。
論文內文中將會比較多條奈米線以及傳統單通道結構的資料寫入以及抹除之特性，明顯地多條奈米線結構能幫助寫入抹除速度，在極短的時間內，即可得到足夠的記憶體窗口(memory window)，此外亦探討此結構的各項可靠度指標，皆明顯指出此結構具有應用於實際產品的高度價值。

Chapter 1
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Chapter 2
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Chapter 3
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