隨著製程圖案越做越小而設計卻越來越複雜的情況下，導致在先進的製程裡設計和量產的鴻溝逐漸變大。
在本篇論文中，我們提出了一個平行的方法來解決以規則為主之佈局圖案搜尋的問題。根據平行現有的有順序的方法，我們不僅維持了原本的解答品質，而且還大幅的減少了原本的方法的運算時間。實驗結果顯示我們所提出的平行化方法具有良好的效益。

As the feature size continues to shrink and the design complexity continues to increase in modern IC industry, the gap between design and manufacturing in advanced technology node becomes larger and larger. In this thesis, we propose a parallel approach for rule-based layout pattern matching problem. By parallelizing an existing sequential work, we not only maintain the solution quality, but also significantly decrease the runtime of the sequential algorithm. Experimental results are reported to support the efficacy of our parallel approach.

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