市場上之儲存裝置以快閃記憶體為主流，其高密度、低成本及低耗能的特性，使得它擁有市場競爭力。然而隨著製程微縮，快閃記憶體面對需要克服的挑戰，例如耦合雜訊干擾以及高偏移臨界電壓。再加上快閃記憶體需要高電壓來進行寫入和消除資料，而且其操作速度偏慢，對於未來更加高速的應用上已不符需求。
一些次世代非揮發性記憶體(例如: 電阻式記憶體、磁阻式記憶體)非常適合用於需要快速讀取和低供給電壓的內嵌式裝置應用上。然而，在大容量的非揮發記憶體中，低阻值率和阻值高偏移的現象會降低感測裕度。
為了在較低的感測裕度下達到更高的感測速度，我們採用了兩段式位元線預充電的方法，降低位元線預充電之時間。並提出具電壓回授架構之電流感測放大器，透過其回授系統增加∕降低源電流之大小，最終達到增加裕度以及快速感測的目標。
在台積電55奈米製程模擬分析下，在大位元線電流之下，我們提出的感測放大器能抑制等效偏移達傳統的6.4~6.6倍，並且具有1.2~1.4倍之感測速度，讀取良率也有7.9%的改善。
我們用台積電55奈米CMOS製程之電阻式記憶體來驗證我們提出的架構。在供給電壓一伏特且位元線長度為512個時，量測到的讀取速度為2.2奈秒。

The storage memory in market with high density, low cost and low energy consumption nowadays is dominated by flash memory. However, it faces several challenges that need to be overcome, such as coupling noise interference and large variation of threshold voltages due to the process shrinks recently. In addition, flash memory requires not only high voltage to write and erase data, but also slow operation speed, which will not be suitable for higher speed applications in the future.
Although some next-generation non-volatile memories (i.e. ReRAM and MRAM) are ideal for in-line device applications which require high performance and low supply voltages. In a large-capacity non-volatile memory, low resistance ratio and large distribution of the resistance value reduce the sensing margin.
In order to achieve a higher sensing speed at a lower sensing margin, we used a two-stage bit line pre-charging method to reduce the bit line pre-charging time. As a result, a current sense amplifier with a voltage feedback architecture is proposed to increase the size of the source current through its feedback system. this also achieves the goal of increasing margin and fast sensing at final.
With the simulation analysis from TSMC's 55nm process, we propose sense amplifier that can suppress equivalent offset and sensing speed by 6.4~6.6 times and 1.2~1.4 times under the large bit line current, respectively. Also, the read yield raises an improvement by 7.9%.
We validate our proposed architecture by using resistive memory under TSMC's 55nm CMOS process. When the supply voltage is one Volt and the bit line length is 512, the measured access time is 2.2 nanoseconds.

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