本次實驗為雙層氮化矽堆疊的溝槽式無接面超薄賦晶矽通道電晶體結合快閃記憶體之研究，主要利用超薄複晶矽通道來提升電晶體部分的電特性，並以此為基礎加上雙層氮化矽堆疊的電荷儲存層(SONNOS)來改善傳統傳統SONOS記憶體較差的電荷儲存能力。本研究的製程簡單且與現金快閃記憶體製程的相容性高，因此很有機會可以應用在未來記憶體元件和高度的三為堆疊技術上。
電晶體特性部分，此元件有著優秀的電特性，而在記憶體部分使用了雙層氮化矽堆疊當作電荷儲存層的結構下，有效的提升了記憶體的各項電特性，在利用穿隧式(FN-tunneling)寫入/抹除機制下，SONNOS結構的元件相對於傳統SONOS元件展現了更優異以及更高良率的表現。此外，在記憶體可靠度的分析上，SONNOS元件依舊表現出了優異的表現。特別是在溫度85°C下模擬十年後的元件儲存電荷能力，SONNOS元件在不論是N通道或是P通道，平面通道結構或是擁有奈米線結構都展現出了趨近於99%的電荷儲存能力。

In this study, the “Double Stacked Si3N4 Flash Memory Based on Ultra-Thin Body Poly-Si Junctionless FET with trench structure”, the characteristics of transistor were improved by ultra-thin channel, and the double stacked Si3N4 was used to improve the poor retention ability of conventional SONOS memory device. Moreover, the fabrication has the simple process and compatible with current Flash memory process. Therefore, it has more opportunity to apply for high density 3D stack technology.
In the point of transistor character, the device has excellent electrical performance, and the part of memory device which was used the double stacked Si3N4 layers as trapping layers that improving the memory characteristics. By FN-tunneling, the SONNOS device present better and higher yield than conventional SONOS device。 Beside, In the reliability of memory device, the SONNOS device also has excellent performance。Especially, the retention characteristic of SONNOS memory device has excellent performance under ten years at 85°C. The device memory windows maintain almost 99% no matter n-channel, p-channel, planar, or Nanowires structure.

Chapter 1
[1-1] Apple buying up available flash RAM supplies for next iPhone
, from (http://www.roughlydrafted.com/2009/02/18/apple-buying-up-available-flash-ram-supplies-for-next-iphone/)

[1-2] Thomas Friedman and the Fallacies of Moore’s Law
, from (https://rethinktechnology.wordpress.com/2014/01/16/thomas-friedman-and-the-fallacies-of-moores-law/).

[1-3] Chi-Woo Lee, Isabelle Ferain, Aryan Afzalian, Ran Yan, Nima Dehdashti Akhavan, Pedram Razavi, Jean-Pierre Colinge, “Performance estimation of junctionless multigate transistors,” Solid-State Electronics, vol. 53, pp. 97-103, 2010.
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[1-7] J. P. Colinge, “Semiconductor-On-Insulator Materials for NanoElectronics Applications”, chapter 10, pp.187, 2011.
[1-8] Pavan, Paolo, et al. “Flash memory cells-an overview”, Proceedings of the IEEE 85.8 (1997): 1248-1271.
[1-9] D. Kahng, S. M. Sze, “A floating gate and its application to memory devices”, IEEE Transactions on Electron Devices, Vol. 14, pp. 629-629, 1967.
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[1-20] Vertical 3D NAND Possible by 2013-2014 By David Lammers, SemiMD, from(http://www.semi.org/en/node/38361).

[1-21] Park, J. K., Kim, S. Y., Lee, K. H., Pyi, S. H., Lee, S. H., & Cho, B. J. “Surface-controlled ultrathin (2 nm) Poly-Si channel junctionless FET towards 3D NAND flash memory applications”. VLSI Technology (VLSI-Technology): Digest of Technical Papers, pp. 1-2. 2014.

[1-22] Kim, B., Lim, S. H., Kim, D. W., Nakanishi, T., Yang, S., Ahn, J. Y., ... & Kang, C. J. “Investigation of ultra thin polycrystalline silicon channel for vertical NAND flash”, In Reliability Physics Symposium (IRPS), pp. 2E-4. 2011.
[1-23] Yeh, M. S., Wu, Y. C., Wu, M. H., Jhan, Y. R., Chung, M. H., & Hung, M. F. (2014, December). “High performance ultra-thin body (2.4 nm) poly-Si junctionless thin film transistors with a trench structure”, In Electron Devices Meeting (IEDM), pp. 26-6. 2014.

Chapter 2
[2-1] P. Pavan, R. Bez, P. Olivo, E. Zanoni, “Flash memory cells-an overview”, Proceedings of the IEEE, Vol. 85, pp. 1248, 1997.
[2-2] M. Lenzlinger, E. H. Snow, “Fowler‐Nordheim Tunneling into Thermally Grown SiO2”, J. Appl. Phys., Vol. 40, 1, 2003.
Chapter 3
[3-1] Yeh, M. S., Wu, Y. C., Wu, M. H., Jhan, Y. R., Chung, M. H., & Hung, M. F. (2014, December). “High performance ultra-thin body (2.4 nm) poly-Si junctionless thin film transistors with a trench structure”, In Electron Devices Meeting (IEDM), pp. 26-6. 2014.

Chapter 4
[4-1] Park, J. K., Kim, S. Y., Lee, K. H., Pyi, S. H., Lee, S. H., & Cho, B. J. “Surface-controlled ultrathin (2 nm) Poly-Si channel junctionless FET towards 3D NAND flash memory applications”. VLSI Technology (VLSI-Technology): Digest of Technical Papers, pp. 1-2. 2014.
[4-2] Kim, B., Lim, S. H., Kim, D. W., Nakanishi, T., Yang, S., Ahn, J. Y., ... & Kang, C. J. “Investigation of ultra thin polycrystalline silicon channel for vertical NAND flash”, In Reliability Physics Symposium (IRPS), pp. 2E-4. 2011.