研究生: |
洪志文 Hung, Chih-Wen |
---|---|
論文名稱: |
快閃記憶體轉換層高速模擬器之開發及運用 Development and Deployment of a Fast Flash Translation Layer Simulator |
指導教授: |
呂仁碩
Liu, Ren-Shuo |
口試委員: |
許雅三
Hsu, Yarsun 呂仁碩 Liu, Ren-Shuo 劉靖家 Liou, Jing-Jia |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
論文出版年: | 2017 |
畢業學年度: | 105 |
語文別: | 英文 |
論文頁數: | 37 |
中文關鍵詞: | 快閃記憶體 、快閃記憶體轉換層 、固態硬碟 、模擬器 |
外文關鍵詞: | NAND Flash Memory, Flash Translation Layer (FTL), Solid-State Drive (SSD), Simulator |
相關次數: | 點閱:2 下載:0 |
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固態硬碟(solid state drive, SSD)是現今最重要的儲存技術,其中快閃記憶體轉換層(flash translation layer, FTL)是最核心的韌體元件。學界與業界為了增進SSD的效能,一直持續開發創新的FTL設計,包括邏輯與物理位置轉換、冷熱資料分離、耗損平均等,因此使FTL的複雜度持續增加。這個趨勢使FTL變得越來越容易因疏忽而隱含韌體上設計的瑕疵(bugs)。這些瑕疵如果沒有在設計製造階段被發掘,待SSD銷售之後,可導致例如使用者資料毀損這類嚴重的後果。這是SSD設計與製造很大的挑戰。
我們提出一個能在電腦或伺服器上執行SSD的FTL程式碼,幫助韌體工程師發掘FTL瑕疵的功能模擬器(functional simulator):FTLburn。FTLburn利用電腦或伺服器的主記憶體模擬SSD的靜態隨機存取記憶體(SRAM)、動態隨機存取記憶體(DRAM)、及快閃記憶體。工程師幾乎不須要修改SSD產品所使用的FTL程式碼,就可以藉由我們所開發的FTLburn模擬器,將FTL編譯成電腦或伺服器可執行的執行檔。FTLburn模擬器讓工程師可以快速且大量地對FTL程式碼測試,非常適合用來強化傳統設計流程中使用真實SSD硬體來測試FTL韌體的步驟。我們將FTLburn運用在知名的SSD專案:OpenSSD。在四核心的電腦環境下,FTLburn可以用高達110 GB/s的存取速度測試FTL,比使用SATA 3.0 (600 MB/s)介面的真實SSD測試速度快180倍。更重要的,我們確實利用FTLburn找出多個OpenSSD專案中未曾被發現的韌體瑕疵,這是本論文FTLburn模擬器效用的最佳佐證。
A flash translation layer (FTL) is the core firmware component of NAND flash-based solid state drives (SSDs), which are among the most important storage technology nowadays. Academia and industry have been continuously innovating new FTL strategies to enhance SSDs, such as address mapping, wear-leveling, and hot-cold data separation. The increasing complexity of FTLs and the pursuit of high-performance FTLs have brought big challenges to SSD manufacturers that FTL firmware becomes increasingly more prone to bugs, which can result in catastrophic data losses if not found during design and development.
This work proposes FTLburn, a functional simulator for FTLs, to allow engineers to \emph{compile and execute native SSD FTL code on PCs or servers} against emulated SRAM, DRAM, and flash capacity. FTLburn enables fast and massive SSD burn-in tests with the focus on FTLs. Therefore, FTLburn is an ideal framework to improve the conventional SSD and FTL design flow, in which burn-in tests are performed against real SSD hardware. We apply FTLburn to a well-known SSD project, OpenSSD. FTLburn not only achieves high burn-in throughput up to 110 GB/s on a four-core PC, which is $180\times$ faster than performing burn-in tests on an SSD with an SATA 3.0 (600 MB/s) interface; more importantly, as a solid proof of effectiveness, FTLburn enables us to discover many new FTL firmware bugs in the OpenSSD project.
[1] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, “Introduction to flash memory,”
Proceedings of the IEEE, vol. 91, no. 4, pp. 489–502, 2003.
[2] E. Gal and S. Toledo, “Algorithms and data structures for flash memories,” ACM
Computing Surveys (CSUR), vol. 37, no. 2, pp. 138–163, 2005.
[3] P. Cappelletti and A. Modelli, “Flash memory reliability,” in Flash Memories,
pp. 399–441, Springer, 1999.
[4] A. Birrell, M. Isard, C. Thacker, and T. Wobber, “A design for high-performance
flash disks,” SIGOPS Oper. Syst. Rev., vol. 41, pp. 88–93, April 2007.
[5] S.-P. Lim, S.-W. Lee, and B. Moon, “FASTer FTL for enterprise-class flash memory
SSDs,” in Workshop on Storage Network Architecture and Parallel I/ Os
(SNAPI), 2010.
[6] A. Gupta, Y. Kim, and B. Urgaonkar, “DFTL: a flash translation layer employing
demand-based selective caching of page-level address mappings,” in Architectural
Support for Programming Languages and Operating Systems (ASPLOS), 2009.
[7] “Intel confirms 8MB bug in 320 series SSDs.” http://www.techspot.com/news/
44694-intel-confirms-8mb-bug-in-320-series-ssds-fix-available.html, Aug. 2011.
[8] “Crucial acknowledges weird 5,000 hour M4 SSD bug, promises firmware fix in
mid-January.” http:// hothardware.com/ news/ crucial-acknowledges-weird-5000-
hour-m4-ssd-bug-promises-firmware-fix-in-midjanuary, Jan. 2012.
[9] A. L. Shimpi, “SandForce identifies firmware bug causing BSOD issue, fix
available today.” http:// www.anandtech.com/ show/ 4973/ sandforce-identifiesfirmware-
bug-causing-bsod-issue-fix-available-today, Oct. 2011.
[10] “PassMark BurnInTest.” http://www.passmark.com/products/bit.htm.
[11] “Jasmine OpenSSD platform.” http:// www.openssd-project.org/
wiki/Jasmine_OpenSSD_Platform.
[12] S.-W. Lee, D.-J. Park, T.-S. Chung, D.-H. Lee, S. Park, and H.-J. Song, “A
log buffer-based flash translation layer using fully-associative sector translation,”
ACM Transactions on Embedded Computing Systems (TECS), vol. 6, no. 3, p. 18,
2007.
[13] N. Agrawal, V. Prabhakaran, T. Wobber, J. D. Davis, M. Manasse, and R. Panigrahy,
“Design tradeoffs for SSD performance,” in USENIX Annual Technical
Conference (USENIX ATC), 2008.
[14] Y. Kim, B. Tauras, A. Gupta, and B. Urgaonkar, “Flashsim: A simulator for nand
flash-based solid-state drives,” in International Conference on Advances in System
Simulation (SIMUL), 2009.
[15] M. Jung, E. H. Wilson, D. Donofrio, J. Shalf, and M. T. Kandemir, “NANDFlash-
Sim: Intrinsic latency variation aware NAND flash memory system modeling and
simulation at microarchitecture level,” in Symposium on Mass Storage Systems
and Technologies (MSST), 2012.
[16] J. S. Bucy, J. Schindler, S. W. Schlosser, and G. R. Ganger, “The DiskSim simulation
environment version 4.0 reference manual reference manual (CMU-PDL-
08-101),” tech. rep., Parallel Data Laboratory, 2008.
[17] R.-S. Liu, C.-L. Yang, and W. Wu, “Optimizing NAND flash-based SSDs via
retention relaxation,” in USENIX Conference on File and Storage Technologies
(FAST), 2012.
[18] R.-S. Liu, M.-Y. Chuang, C.-L. Yang, C.-H. Li, K.-C. Ho, and H.-P. Li, “EC-Cache:
Exploiting error locality to optimize LDPC in NAND flash-based SSDs,” in Design
Automation Conference (DAC), 2014.
[19] R.-S. Liu, M.-Y. Chuang, C.-L. Yang, C.-H. Li, K.-C. Ho, and H.-P. Li, “Improving
read performance of NAND flash SSDs by exploiting error locality,” IEEE
Transactions on Computers, vol. 65, pp. 1090–1102, April 2016.
[20] M.-L. Chiang, P. C. H. Lee, and R.-C. Chang, “Using data clustering to improve
cleaning performance for plash memory,” Softw. Pract. Exper., vol. 29, pp. 267–
290, Mar. 1999.
[21] Y. Cai, O. Mutlu, E. F. Haratsch, and K. Mai, “Program interference in mlc nand
flash memory: Characterization, modeling, and mitigation,” in International Conference
on Computer Design (ICCD), 2013.
[22] D. Narayanan, A. Donnelly, and A. Rowstron, “Write off-loading: Practical
power management for enterprise storage,” Trans. Storage, vol. 4, pp. 10:1–10:23,
November 2008.