隨著微機電系統發展不斷推陳出新，利用標準平台發展出相關元件，始終成為此領域之關鍵技術。透過CMOS-MEMS製程技術，同時整合微結構與感測電路在同一晶片上，不僅可以利用半導體本身可縮小線寬、批量製造與系統整合優勢，也能提高其附加價值，因此，相關技術之發展重要性不可言喻。
本研究欲利用TSMC 0.35 μm 2P4M標準CMOS製程平台來設計出電容式感測晶片，以加速度計作為研究主軸，在結構設計部分，針對一般CMOS-MEMS加速度計進行設計改良與效能提升，分別設計出兩種改良型態的加速度計結構。第一種為具有選擇性電鍍鎳於CMOS晶片上，具以下三個特色：(i)選擇性電鍍可藉由CMOS與MEMS標準製程實現，(i)電鍍鎳結構厚度可改善質量塊重量與結構剛性，進而抑制結構對溫度效應的敏感性，(iii)電鍍後製程為常溫製程，不會影響CMOS金屬層與感測電路，綜合以上優點成功提升加速度計效能(例如靈敏度、雜訊準位以及最小可偵測訊號)。第二種改良型態加速度計為利用單層二氧化矽材料作為CMOS-MEMS加速度計結構，具有以下四個特色：(i)降低MEMS結構懸浮後因殘餘應力所產生的初始形變，(ii)抑制複合膜層因熱膨脹係數不同所產生的形變量，(iii)在純二氧化矽質量塊中電性的繞線可以大幅降低寄生電容進而提升感測靈敏度，(iv)低溫度效應未來可相容於封裝溫度，綜合以上優點使其具有高靈敏度與低熱飄移。
此外，在電容感測介面電路提出多通道(Multi-channel)感測機制讀取多軸感測器訊號，具有以下三個特色：(i)加速度感測器結構電性透過全差分電性連結，可有效抑制共模雜訊，(ii)感測電路透過時脈切換的方式對感測器訊號進行讀取，使整顆晶片具有高訊雜比與小尺寸特色，(iii)此電路架構可整合其他電容式感測器例如三軸陀螺儀與三軸磁力計，使單晶片系統有最小晶片面積。

There are many different fabrication processes for Micro-Electro-Mechanical System (MEMS). However, the standard fabrication process is a major factor which plays an important role in MEMS. In this study, a capacitive sensing chip is proposed to use TSMC 0.35 μm 2-polysilicon 4-Metal (2P4M) standard process. Two novel designs together with capacitive interface circuitry of accelerometers were respectively proposed in thesis.
First study presents a simple approach to improve the performance of CMOS-MEMS capacitive accelerometer by means of the post-CMOS metal electroplating process. The metal layer can be selectively electroplated on the MEMS structures at low temperature; and the thickness of metal layer can be easily adjusted by process. Thus, the performance of capacitive accelerometer (i.e., structure deformation, sensitivity) can be improved significantly.
Second study proposed the stacking of pure oxide layers as the mechanical structures for CMOS-MEMS accelerometer has been developed and demonstrated for the first time. Thus, the distribution of metal-oxide composites in CMOS-MEMS accelerometer is changed from area to line. Such design has the following advantages to solve the initial deformation of suspended MEMS structures due to the residual stresses of metal-oxide films, as well as the thermal deformation of suspended MEMS structures due to the thermal expansion coefficient (CTE) mismatch of metal-oxide films. The parasitic capacitance of sensing electrodes routing underneath the proof-mass also can be further reduced. In addition, the CMOS multi-channel readout circuit on a single chip was developed to sense the time-varient sensing signal. Thus, the smallest footprint of chip size can be achieved.

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