這篇論文呈現了一個非二位元低密度奇偶檢查碼高吞吐量解碼器架構，
是基於Log-QSPA演算法。首先，為了使檢查點(check node)可以有效率的運
算，我們針對了檢查點更新程序(check node processing)做了數學公式上運算
的重新排列，使得檢查點更新程序能夠用有效率的籬柵方法來表現，而在
籬柵配置方法中使用了向前訊息(forward message)以及向後訊息(backward
message)來做檢查點更新程序。為了增加解碼的吞吐量，使用了雙方向前向
後遞迴(bidirectional forward-backward recursion)。除此之外，分層式解碼也
被採用來增加解碼的收斂速度。最後，一個訊息上的壓縮技巧被使用來減
少硬體上儲存的空間要求，進一步來節省面積。在硬體呈現，使用了90-nm
CMOS 製程來實現一個在GF(32)下(837,726)的非二位元低密度奇偶檢查碼
解碼架構來呈現我們的想法。這個解碼器能夠達到233.53 Mbps的吞吐量當
使用時脈頻率為250 MHz的時候。比起以往的非二位元低密度奇偶檢查碼解
碼架構，在類似的錯誤率效能，此解碼器能夠達到最高的吞吐量。

This paper presents a high-throughput decoder architecture for non-binary
low-density parity-check (LDPC) codes, where the q-ary sum-product algo-
rithm (QSPA) in the log domain is considered. We reformulate the check-node
processing such that an efficient trellis-based implementation can be used,
where forward and backward recursions are involved. In order to increase the
decoding throughput, bidirectional forward-backward recursion is used. In ad-
dition, layered decoding is adopted to reduce the number of iterations based
on a given performance. Finally, a message compression technique is used to
reduce the storage requirements and hence the area. Using a 90-nm CMOS
process, a 32-ary (837,726) LDPC decoder was implemented to demonstrate
the proposed techniques and architecture. This decoder can achieve a through-
put of 233.53 Mbps at a clock frequency of 250 MHz based on the post-layout
results. Compared to the decoders presented in previous literature, the pro-
posed decoder can achieve the highest throughput based on a similar/better
error performance.

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