本研究主要提出一個串化-解串化器(SerDes)以及資料時脈還原電路(CDR)來達成高速的資料處理在有線通訊系統之應用。
所設計的二對一多功器與一對二多功器為處理最高40 Gb/s資料傳輸速度。相較於傳統的電流型邏輯電路(CML)，變壓器耦合電流(TCC)的電路被設計成更高的源級電流(Drain Currnet)和更低的供應電壓(Supply Voltage)。這兩顆晶片以65nm CMOS製程製作出，消耗低於一百毫瓦(<100 mW)並且操作在0.8伏特的提供電壓。經過串化及解串化的40 Gb/s的 2^7–1虛擬隨機二進位序列資料驗證了串化與解串化界面的功能。
所設計的線性資料時脈還原電路(CDR)操作在全速式2.56/3.2Gb/s資料。延展式相位偵測器(EPD)用來取代傳統Hogge的相位偵測器。資料時脈還原電路在0.18-μm CMOS製程實作出和0.8×1.0 mm^2晶片面積。這個晶片展現出一個方均根2.12 ps低抖動的還原時脈和在　2３１ – 1虛擬隨機二進位序列的3.5 × 10^-9錯誤更正率。在提供電壓1.8伏特下消耗136 mW。
　　所設計的二進位資料時脈還原電路(CDR)操作在全速式10Gb/s資料。所提出的旋轉式相位頻率偵測器(RPFD)用在無參考時脈的資料還原電路。單一迴路之資料時脈還原電路以90nm CMOS製程製作出0.71-mm^2晶片尺寸。在10-Gb/s的2^31–1虛擬隨機二進位序列下，資料時脈還原電路追蹤1.48 GHz捕捉範圍之自由時脈訊號並且鎖定於20 μs的追蹤時間。同時間，還原時脈訊號和還原資料訊號的峰對峰值抖動分別展現出5 ps和15.11 ps。在提供電壓1.0伏特下量測的晶片消耗了92 mW。

The thesis proposes a serializer-and-deserializer (SerDes) with a clock and data recovery (CDR) to achieve high speed data processing for the wire-line communication system.
The proposed 2:1 MUX and 1:2 DEMUX design deals with the maximum 40 Gb/s data transmission rate. A transformer-coupled current (TCC) schematics is designed to more drain current and less supply voltage than the current-mode-logic (CML). The two chips are implemented in 65 nm standard CMOS technology and consume sub-hundred milliwatt operation power at the supply voltage of 0.8-V. The measured serialized-and-deserialized 40-Gb/s PRBS of 2^7–1 verify the function of SerDes interface.
The proposed linear-type CDR design operates at full-rate data of 2.56/3.2Gb/s. An Ex-tended Phase Detector (EPD) circuit is proposed to replace the Hogge`s PD. The CDR circuit is fabricated in a 0.18μm 1P6M CMOS process in an area of 0.8×1.0 mm^2. This CDR chip exhibits a low jitter performance of 2.12 ps RMS in the recovered clock and a BER is 3.5 × 10^-9 with PRBS of 2^31–1 sequence. The power consumption is 136mW with a 1.8V supply.
The proposed binary-type CDR design operates at full-rate 10 Gb/s data. A rotational phase frequency detector (RPFD) is proposed to realize reference-less CDR. The single-loop CDR is fabricated in TSMC mixed-signal 1P9M 90-nm standard CMOS process with overall die size of 0.71-mm^2. With input 10-Gb/s data of a 2^31–1 PRBS, the CDR tracks free running clock over the capture range of 1.48 GHz and locks in the acquisition time of 20 μs. At the same time, the peak-to-peak jitter shows only 5.0 ps in the recovered clock and exhibits 15.11 ps in the recovered data. The measured chip consumes 92 mW with 1.0-V supply voltage.

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