研究生: |
彭煥凱 Huan-Kai Peng |
---|---|
論文名稱: |
適用於多服務項目系統晶片溝通架構之即時仲裁演算法 A Realtime Arbitration Algorithm for On-Chip Multi-QoS Communication |
指導教授: |
林永隆
Youn-Long Lin |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 資訊工程學系 Computer Science |
論文出版年: | 2007 |
畢業學年度: | 95 |
語文別: | 英文 |
論文頁數: | 42 |
中文關鍵詞: | 即時 、仲裁 、服務項目 |
外文關鍵詞: | Realtime, Arbitration, QoS |
相關次數: | 點閱:2 下載:0 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
隨著系統晶片科技的發展,越來越多的矽智財可以藉由分享式的系統溝通架構整合於單一系統晶片之上。由於不同的矽智財會要求系統溝通架構提供不同的服務品質項目,因此系統溝通架構上的仲裁演算法的設計日益複雜。
在有即時性要求的系統晶片中,即時性保證是其溝通架構中第一優先的品質項目。但若一昧地使用即時性演算法來做仲裁,將難以確保其他非即時性的服務項目。因此,在此種應用中,須要特殊的即時性保證演算法來同時兼顧即時性及非即時性的各種服務項目。
本論文提出一準確且適合硬體實作的即時保證仲裁演算法。透過數學定理推導,此演算法可在確保即時性的狀況下,最大化使用非即時性演算法的機會。本論文也討論了實作上此演算法法與不同應用中的非即時演算法,在整合時應做的考量,並以分析方式說明此演算法在時序及硬體面積成本方面皆為低複雜度。
實驗結果顯示,本演算法減低了百分之三十八的即時阻擋率,大量提高了非即時性演算法使用的機會。在搭配一廣泛使用的非即時性演算法下,此即時性演算法協助降低了百分之十八的時脈消耗。實作後,此演算法僅需不到五千個邏輯閘門,並且其時脈可達到兩百五十百萬赫茲以上。因此,此演算法表現良好並可廣泛的使用在一般系統晶片中。
In an advanced System-on-Chip (SoC) for realtime applications, the arbitration algorithm of the on-chip communication architecture needs to support multiple non-realtime QoS criterions while ensuring hard realtime guarantee. To fulfill both, the arbitration algorithm must dynamically switch between non-realtime and realtime modes such that any unnecessary use of the later is eliminated to better satisfy the former. In this work, we isolate the problem to the warning line assignment problem and derive the optimal solution. Practical techniques and issues are addressed for general SoC applications. Experimental results show that using the proposed scheme, the number of times switching to the realtime mode is reduced up to 38%. Also, it helps reduce the execution time by as much as 18% when applied together with a commonly used arbitration policy. Finally, the hardware implementation is shown to be of low area cost and high operating frequency, which makes it applicable in SoC applications.
[1] C. L. Liu, and J. W. Layland. Scheduling algorithms for multiprogramming in a hard-healtime environment. In Journal of the Association for Computing Machinery, 20(1):46–61, January 1973.
[2] R. R. Howell and M. K. Venkatrao. On non-preemptive scheduling of recurring tasks using inserted idle times. In Information and Computation, 117(1):50-62, February 1995.
[3] K. Jeffay, D. F. Stanat, and C. U. Martel. On non-preemptive scheduling of periodic and sporadic tasks. In Proceedings of 12th IEEE Real-Time Systems Symposium, pages 129-139, San Antonio (TA), U.S.A., December 1991.
[4] L. George, P. Muhlethaler, and N. Rivierre. Optimality and non-preemptive real-time scheduling revisited. In INRIA Research Report n□2516, April 1995.
[5] V. Swaminathan and K. Chakrabarty, Pruning-based, energy-optimal, deterministic I/O device scheduling for hard real-time systems. In ACM Transactions on Embedded Computing Systems, 4(1):141–167, February 2005.
[6] L. George, P. Muhlethaler, and N. Rivierre. A few results on non-preemptive real time scheduling. In INRIA Research Report n□3926, May 2000.
[7] L. Sha, T. Abdelzaher, K. Arzen, A. Cervin, T. Baker, A. Burns, G. Buttazzo, M. Caccamo, J. Lehoczky, and A. K. Mok. Real time theory: a historical perspective. In Realtime Systems, 28:101-155, November 2004.
[8] S. Kim, J. Lee, and J. Lee. Runtime feasibility check for non-preemptive real-time periodic tasks. In Information Processing Letters, 97(3):83-87, February 2006.
[9] ARM, Inc. AMBA Specification Rev. 2.0. Available at http://www.arm.com/products/solutions/AMBA_Spec.html, 1999.
[10] IBM, Inc. CoreConnect Bus Architecture version 3.5. Available at http://www-03.ibm.com/chips/products/coreconnect/, 2001.
[11] OpenCores. WISHBONE SoC Interconnection Architecture for Portable IP Cores. Available at http://www.opencores.org/projects.cgi/web/wishbone/wbspec_b3.pdf, 2002.
[12] C. H. Chen, G. W. Lee, J. D. Huang and J. Y. Jou. A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication. In Proceedings of Asia South Pacific Design Automation Conference, pages 600-605, Yokohama, Japan, July 2006.
[13] K. Lahiri, A. Raghunathan and G. Lakshminarayana. LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs. In Proceedings of Design Automation Conference, pages 15-20, Las Vegas, NV, June 2001.
[14] B. C. Lin, G. W. Lee, J. D. Huang, and J. Y. Jou. A precise bandwidth control arbitration algorithm for hard real-time SoC buses. In Proceedings of Asia South Pacific Design Automation Conference, pages 165-170, Yokohama, Japan, January 2007.
[15] Elpeda. How to use SDRAM/DDR/DDR2 - User’s Manual. Available at http://www.elpida.com/en/products/documents.html, 2007
[16] Denali. Databahn™ DRAM Memory Controller IP. Information available at http://www.denali.com/products/databahn_dram.html, 2007.
[17] Micron Technology, Inc. mt48lc16m16a2 256Mb SDRAM. Available at http://www.micron.com/products/datasheet.jsp?Path =/DRAM/ SDRAM&fileID=10, 2003.
[18] K. B. Lee, T. C. Lin, and C. W. Jen. An efficient quality-aware memory controller for multimedia platform SoC. In IEEE Transactions on Circuits and Systems for Video Technology, 15:620-633, May 2005.
[19] T. Takizawa and M. Hirasawa, An efficient memory arbitration algorithm for a single chip MPEG2 AV decoder. In IEEE Transactions on Consumer Electronics, 47-3: 660–665, August 2001.