2.5D集成電路是IC發展的一種新趨勢。 2.5D集成電路在成本的節約上有著許多優勢，這引起了半導體產業對這項技術的龐大興趣。 另一方面，2.5D IC技術已顯示出可以抵禦來自不受信任/惡意的代工廠的智慧財產權（IP）剽竊的能力。
透過混淆2.5D IC中晶片彼此之間的相關性，我們可以承受逆向工程攻擊，並將我們的商業機密保留在中介層中。

在本論文中，我們提出了一種基於超圖雙向分配並考量安全性之2.5D IC切割演算法。我們可以將原始設計簡化為超圖，將邏輯閘描述為超節點，其中內部的導線描述為超邊，再以我們的演算法來定制分割並確定特定導線的來源與接收被分配於兩個不同的分區以確保對特定相關性進行混淆，同時最小化再分配層中的導線數量。
此項目基於n-level超圖分區框架KaHyPar，我們修改了其中的初始分區階段和本地搜索階段以實現我們的要求。

2.5D integration is an IC development trend. There are good economic reasons for the huge interest in 2.5D ICs by the semiconductor industry. On the other hand, 2.5D IC technology has shown the capability to counter Intellectual Property (IP) piracy from untrusted foundries. By obfuscating the correlations between chips in 2.5D ICs, we can withstand reverse-engineering attack and keep our secret in redistribution layers.

In this thesis, we propose a security-aware bipartitoning algorithm for 2.5D IC which is based on hypergraph bipartion.
We could simplify the original design into a hypergraph. The logic gates in the design are depicted as hypernodes, and the wires are depicted as hyperedges. Then we can apply our algorithm to customize the partition and make sure the particular correlations be obfuscated by splitting the source and sinks of the particular edge into two parts, also minimized the number of wires in redistribution layers.
This project is based on the n-Level hypergraph partitioning framework KaHyPar, and we modify the initial partitioning phase and local search phase to achieve our requirements.

[1] Y. Xie, C. Bao, Y. Liu, and A. Srivastava, “2.5 d/3d integration technologies for circuit
obfuscation,” in Microprocessor and SOC Test and Verification (MTV), 2016
17th International Workshop on, pp. 39–44, IEEE, 2016.
[2] T. Heuer, Engineering Initial Partitioning Algorithms for direct k-way Hypergraph
Partitioning. PhD thesis, Karlsruher Institut für Technologie (KIT), 2015.
[3] D. Bryan, “The iscas’85 benchmark circuits and netlist format,” North Carolina
State University, vol. 25, 1985.
[4] C. J. Alpert, “The ispd98 circuit benchmark suite,” in Proceedings of the 1998
international symposium on Physical design, pp. 80–85, ACM, 1998.
[5] M. Rostami, F. Koushanfar, J. Rajendran, and R. Karri, “Hardware security: Threat
models and metrics,” in Proceedings of the International Conference on Computer-
Aided Design, pp. 819–823, IEEE Press, 2013.
[6] Y. Xie, C. Bao, and A. Srivastava, “Security-aware design flow for 2.5 d ic technology,”
in Proceedings of the 5th International Workshop on Trustworthy Embedded
Devices, pp. 31–38, ACM, 2015.
[7] F. Imeson, A. Emtenan, S. Garg, and M. V. Tripunitara, “Securing computer hardware
using 3d integrated circuit (ic) technology and split manufacturing for obfuscation.,”
in USENIX Security Symposium, pp. 495–510, 2013.
[8] J. Valamehr, T. Sherwood, R. Kastner, D. Marangoni-Simonsen, T. Huffmire,
C. Irvine, and T. Levin, “A 3-d split manufacturing approach to trustworthy system
development,” IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, vol. 32, no. 4, pp. 611–615, 2013.
[9] Y. Xie, C. Bao, C. Serafy, T. Lu, A. Srivastava, and M. Tehranipoor, “Security and
vulnerability implications of 3d ics,” IEEE Transactions on Multi-Scale Computing
Systems, vol. 2, no. 2, pp. 108–122, 2016.
[10] S. Schlag, V. Henne, T. Heuer, H. Meyerhenke, P. Sanders, and C. Schulz, “kway
hypergraph partitioning via n-level recursive bisection,” in 18th Workshop on
Algorithm Engineering and Experiments, (ALENEX 2016), pp. 53–67, 2016.
[11] Y. Akhremtsev, T. Heuer, P. Sanders, and S. Schlag, “Engineering a direct k-way
hypergraph partitioning algorithm,” in 19th Workshop on Algorithm Engineering
and Experiments, (ALENEX 2017), pp. 28–42, 2017.
[12] T. Heuer and S. Schlag, “Improving coarsening schemes for hypergraph partitioning
by exploiting community structure,” in 16th International Symposium on Experimental
Algorithms, (SEA 2017), pp. 21:1–21:19, 2017.
[13] T. Heuer, P. Sanders, and S. Schlag, “Network Flow-Based Refinement for Multilevel
Hypergraph Partitioning,” in 17th International Symposium on Experimental
Algorithms (SEA 2018), pp. 1:1–1:19, 2018.
[14] R. Andre, S. Schlag, and C. Schulz, “Memetic multilevel hypergraph partitioning,”
in Proceedings of the Genetic and Evolutionary Computation Conference, GECCO
’18, pp. 347–354, 2018.
[15] B. W. Kernighan and S. Lin, “An efficient heuristic procedure for partitioning
graphs,” The Bell system technical journal, vol. 49, no. 2, pp. 291–307, 1970.
[16] C. M. Fiduccia and R. M. Mattheyses, “A linear-time heuristic for improving
network partitions,” in Proceedings of the 19th design automation conference,
pp. 175–181, IEEE Press, 1982.
[17] T. Semiconductor, “3d-ics and integrated circuit security,” 2008.
[18] K. Vaidyanathan, B. P. Das, E. Sumbul, R. Liu, and L. Pileggi, “Building trusted
ics using split fabrication,” in 2014 IEEE international symposium on hardwareoriented
security and trust (HOST), pp. 1–6, IEEE, 2014.
[19] K. Vaidyanathan, B. P. Das, and L. Pileggi, “Detecting reliability attacks during
split fabrication using test-only beol stack,” in Design Automation Conference
(DAC), 2014 51st ACM/EDAC/IEEE, pp. 1–6, IEEE, 2014.
[20] M. Jagasivamani, P. Gadfort, M. Sika, M. Bajura, and M. Fritze, “Split-fabrication
obfuscation: Metrics and techniques,” in Hardware-Oriented Security and Trust
(HOST), 2014 IEEE International Symposium on, pp. 7–12, IEEE, 2014.
[21] C. T. O. Otero, J. Tse, R. Karmazin, B. Hill, and R. Manohar, “Automatic obfuscated
cell layout for trusted split-foundry design,” in Hardware Oriented Security
and Trust (HOST), 2015 IEEE International Symposium on, pp. 56–61, IEEE,
2015.
[22] Y. Wang, P. Chen, J. Hu, G. Li, and J. Rajendran, “The cat and mouse in split manufacturing,”
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
vol. 26, no. 5, pp. 805–817, 2018.
[23] J. Magaña, D. Shi, J. Melchert, and A. Davoodi, “Are proximity attacks a threat
to the security of split manufacturing of integrated circuits?,” IEEE Transactions
on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 12, pp. 3406–3419,
2017.
[24] P.-L. Yang and M. Marek-Sadowska, “Making split-fabrication more secure,” in
Computer-Aided Design (ICCAD), 2016 IEEE/ACM International Conference on,
pp. 1–8, IEEE, 2016.
[25] J. Rajendran, M. Sam, O. Sinanoglu, and R. Karri, “Security analysis of integrated
circuit camouflaging,” in Proceedings of the 2013 ACM SIGSAC conference on
Computer & communications security, pp. 709–720, ACM, 2013.
[26] M. Yasin, B. Mazumdar, O. Sinanoglu, and J. Rajendran, “Camoperturb: secure ic
camouflaging for minterm protection,” in Computer-Aided Design (ICCAD), 2016
IEEE/ACM International Conference on, pp. 1–8, IEEE, 2016.
[27] C. Yu, X. Zhang, D. Liu, M. Ciesielski, and D. Holcomb, “Incremental satbased
reverse engineering of camouflaged logic circuits,” IEEE Transactions
on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 10,
pp. 1647–1659, 2017.
[28] G. T. Becker, F. Regazzoni, C. Paar, and W. P. Burleson, “Stealthy dopant-level
hardware trojans,” in International Workshop on Cryptographic Hardware and
Embedded Systems, pp. 197–214, Springer, 2013.
[29] Y. Bi, P.-E. Gaillardon, X. S. Hu, M. Niemier, J.-S. Yuan, and Y. Jin, “Leveraging
emerging technology for hardware security-case study on silicon nanowire fets and
graphene symfets,” in Test Symposium (ATS), 2014 IEEE 23rd Asian, pp. 342–347,
IEEE, 2014.
[30] S. Chen, J. Chen, D. Forte, J. Di, M. Tehranipoor, and L. Wang, “Chip-level antireverse
engineering using transformable interconnects,” in Defect and Fault Tolerance
in VLSI and Nanotechnology Systems (DFTS), 2015 IEEE International
Symposium on, pp. 109–114, IEEE, 2015.
[31] J. Rajendran, O. Sinanoglu, and R. Karri, “Is split manufacturing secure?,” 2013
Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1259–
1264, 2013.
[32] R. Diekmann, R. Preis, F. Schlimbach, and C. Walshaw, “Shape-optimized mesh
partitioning and load balancing for parallel adaptive fem,” Parallel Computing,
vol. 26, no. 12, pp. 1555–1581, 2000.
[33] G. Karypis and V. Kumar, “A fast and high quality multilevel scheme for partitioning
irregular graphs,” SIAM Journal on scientific Computing, vol. 20, no. 1,
pp. 359–392, 1998.
[34] S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, “Optimization by simulated annealing,”
science, vol. 220, no. 4598, pp. 671–680, 1983.