多向閘極與超薄主動層之12奈米無接面式場效電晶體的研究

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研究生：	詹易叡 Jhan, Yi-Ruei
論文名稱：	多向閘極與超薄主動層之12奈米無接面式場效電晶體的研究 Multi-Gate and Ultra-Thin Active Layer of 12 nm Junctionless Field-Effect Transistors
指導教授：	吳永俊
口試委員:	張廖貴術林育賢
學位類別：	碩士 Master
系所名稱：	原子科學院 - 工程與系統科學系 Department of Engineering and System Science
論文出版年：	2012
畢業學年度：	100
語文別：	英文
論文頁數：	55
中文關鍵詞：	Junctionless MOSFET 、Multi-Gate
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隨著電子產品不斷日新月異，IC設計必定要朝向高密度發展以符合市場需求，因此元件本身的尺寸也必須不斷微縮來做出回應。然而傳統電晶體由於結構問題導致在微縮上會遭遇相當多的困難，例如短通道效應(Short Channel Effect)以及摻雜困難等。
因此在本研究中，採取了新穎的無接面式結構，此種結構的特色是通道與源極和汲極的摻雜型態相同，摻雜的濃度也相當，因此通道和源極與通道汲極間並無接面存在。當元件在微縮時，因為沒有接面，所以可避免Charge Sharing效應導致的短通道效應。且因為摻雜型態相同，濃度相當，所以在製程上摻雜不再困難，而源極到汲極間也沒有能階差，因此可避免DIBL(Drain Induce Barrier Lowing)效應。
然而無接面式電晶體的關閉特性相當仰賴閘極到通道的能階差，因此要關閉無接面式電晶體不是一件容易的事，所以在此研究中採取了多向閘極的方式來提升閘及控制能力，以期提升關閉特性，比起傳統電晶體可達到更好的次臨界現象，且更適合用來微縮，成為下一個世代的主流電晶體。

As electronic products with each passing day, IC design must be toward the high density development to meet market demand, the size of the components themselves must also be constantly scaling to respond. However, conventional transistors because of structural problems led to encounter considerable difficulties in miniature on the SCE (Short Channel Effect) and random dopant fluctuation.
In this study adopted a novel junctionless structure, the characteristics of such a structure, channel and source and drain of the same doping type, doping concentration is also quite, so the channel to the source electrode and the channel to the drain electrode have no junctions. And it has no Charge Sharing Effect in scaling, because there is no junction to avoid short-channel effect. And doped with the same type, a considerable concentration, the doping process will be easy. There have no energy level difference between gate to channel so that can be avoided DIBL (Drain Induce Barrier Lowing) effect.
However, the off state characteristic of junctionless transistor depend on the energy level difference between gate to channel, therefore to shut down the junctionless transistor is not an easy thing, so in this study adopted the multi gate to improve the gate control ability. That achieved better subthreshold characteristics in the off state, and more suitable for scaling, to become the next generation of mainstream transistor.

Contents..............................................vii

Table Captions.......................................viii

Chapter 3............................................viii

Chapter 5............................................viii

Figure Captions........................................ix

Chapter 1..............................................ix

Chapter 2..............................................ix

Chapter 3..............................................ix

Chapter 4...............................................x

Chapter 1...............................................1

Introduction............................................1

1.1 Introduction to Conventional Field Effect Transistors    ........................................................1

1.1.1 The Challenges of Conventional Field Effect Transistors.............................................4

1.2 Motivation..........................................7

1.3 Thesis Organization.................................7

Chapter 2...............................................8

Basic Mechanisms of Junctionless Field Effect Transistors    ........................................................8

2.1 Introduction........................................8

2.2 Basic Mechanisms of Junctionless Field Effect Transistors............................................10

2.2.1 Nanowire structure and Ultra-Thin Body...........13

2.3 Trigate and Gate-All-Around Structure..............15

Chapter 3..............................................17

Device Structure and Simulation........................17

3.1 Device Structure and Simulation....................17

Chapter 4..............................................22

Results and Discussions................................22

4.1 Trigate Junctionless Field Effect Transistors......22

4.1.1 Adjustment of Doping Concentration...............27

4.1.2 Adjustment of Oxide Thickness....................29

4.1.3 Adjustment of Channel Square with Width..........31

4.1.4 Adjustment of Gate Length........................33

4.2 Gate-All-Around Junctionless Field Effect Transistors    .......................................................35

4.2.1 Adjustment of Doping Concentration...............39

4.2.2 Adjustment of Oxide Thickness....................41

4.2.3 Adjustment of Channel Square with Width..........43

4.2.4 Adjustment of Gate Length........................45

4.3 The Comparison of Short Channel Effect.............47

Chapter 5..............................................51

Conclusions............................................51

Reference..............................................53

Chapter 1
[1-1] S. M. SZE, KWOK K. NG, “Physics of Semiconductor Devices” 3rd Ed., ch. 6, New Jersey: Wiley-InterScience, 2007.
[1-2] J. E. Lilienfeld, "Method and Apparatus for Controlling Electric Current," U.S. Patent 1,745,175. Filed 1926. Granted 1930.
[1-3] J. E. Lilienfeld, "Amplifier for Electric Current," U.S. Patent 1,877,140. Filed 1928. Granted 1932.
[1-4] J. E. Lilienfeld, "Device for Controlling Electric Current," U.S. Patent 1,900,018. Filed 1928. Granted 1933.
[1-5] 0. Heil, “Improvement in or Relating to Electric Amplifiers and other Control Arrangements and Devices,” British Patent 439,457. Filed and granted 1935.
[1-6] W. Shockley and G. L. Pearson, “Modulation of Conductance of Thin Films of Semiconductors by Surface Charges,” Phy. Rev., 74, 232 (1948).
[1-7] D. Kahng, “A Historical Perspective on the Development of MOS Transistors and Related Devices,” IEEE Trans. Electron Dev., ED-23, 655 (1976).
[1-8] C. T. Sah, “Evolution of the MOS Transistor-From Conception,” Proc. IEEE, 76, 1280 (1988).
[1-9] B. G. Streetman and S. K. Banerjee, “Solid State Electronic Device” 6th Ed., ch. 6, Pearson Prentice Hall, New Jersey, 2006.
[1-10] Alexei Nazarov, J. –P. Colinge, F. Balestra, J. P. Raskin, F. Gamiz and V. S. Lysenko, “Semiconductor-On-Insulator Materials ” 6th Ed., ch. 6, Pearson Prentice Hall, New Jersey, 2006.

Chapter 2
[2-1] J. -P. Colinge et al., “Nanowire transistors without junctions” Nature Nanotechnology 5. 225, 2010.
[2-2] J. -P. Colinge, Isabelle Ferain, Abhinav Kranti, Chi-Woo Lee, Nima Dehdashti Akhavan, Pedram Razavi and Ran Yu, “Junctionless Nanowire Transistor：Complementary Metal-Oxide-Semiconductor Without Junctions,” Science of Advanced Materials, vol. 3, 477-482, 2011.
[2-3] S. Cristoloveanu and S. Williams, “Point Contact Pseudo MOSFET In-Situ Characterization of As-Grown Silicon-On-Insulator,” IEEE Electron Device Letters, vol. 13, no.2, Feb. 1992.
[2-4] C. W. Lee, A. Borne, I. Ferain, A. Afzalian, R. Yan, N. Dehdashti, and J. P. Colinge, “High-Temperature Performance of Silicon Junctionless MOSFETs,” IEEE Transactions on Electron Devices, vol. 57, pp. 620-625, 2010.
[2-5] H. C. Lin, C. I. Lin, T. Y. Huang, “Characteristics of n-Type Junctionless Poly-Si Thin-Film Transistors With an Ultrathin Channel,” IEEE Electron Device Letters, vol. 33, no.1, Feb. 2012.

Chapter 4
[4-1] J. –P. Colinge et al., “Reduced Electric Field In Junctionless Transistors,” Appl. Phys. Lett., Vol. 96, pp. 073510 - 073510-3, 2010 .

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