在本論文中，提出完全不需要額外光罩的新型垂直邏輯相容雙極性電晶體，其具有高增益以及可微縮的特性，並成功驗證利用此新型雙極性電晶體驅動之立體垂直電阻式記憶體，可達成記憶體高效與高密度的需求。
垂直雙極性電晶體的形成主要是利用在N-Well(或P-Well)中打Core N-LDD及其P-Pocket(或Core P-LDD及其N-pocket)的摻雜，形成垂直的NPN(或PNP)結構。以NPN雙極性電晶體為例，表層濃度高的Core N-LDD為雙極性電晶體之射極，濃度低且佈植較深的P-Pocket為基極，N-Well為集極。文中主要是關於NPN雙極性電晶體的討論，大致分成將基極P-Pocket接出表面之P＋接點與I/O P-LDD接點結構，以及其相關結構變數的探討與應用在電阻式記憶體驅動之陣列佈局。
藉由在新型雙極性電晶體射極之上形成堆疊的電阻性記憶體薄膜TiN/Ti/HfO2/TiN，形成1BJT+1R的立體垂直電阻式記憶體結構。相較於金氧半電晶體當驅動器，藉由高增益的雙極性電晶體驅動，立體垂直電阻式記憶體可以節省面積且降低操作電壓，並具有高效且高密度的特性。

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