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研究生: 顏玄德
Yen, Hsuan-Der
論文名稱: CMOS 射頻/毫米波電路設計與可靠性分析之研究
Design and Reliability Studies of CMOS RF/Millimeter Wave Circuits
指導教授: 徐永珍
Hsu, Yung-Jane
葉鳳生
Huang, Fon-Shan
口試委員: 郭建男
Chien-Nan Kuo
葉文冠
Wen-Kuan Yeh
葉鳳生
Fon-Shan Huang
徐永珍
Klaus Yung-Jane Hsu
黃國威
Guo-Wei Huang
學位類別: 博士
Doctor
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2014
畢業學年度: 102
語文別: 英文
論文頁數: 80
中文關鍵詞: 功率放大器混波器壓控震盪器低功率射頻電路功率低電壓熱載子金氧半場效電晶體吉伯特毫米波可靠度閘極氧化崩潰E類串疊組態輸出功率低功率消耗
外文關鍵詞: Power Amplifier, mixer, voltage control oscillator, low power, RF circuit, Power, low voltage, hot carrier, Complementary metal-oxide-semiconductor, Gilbert, millimeter wave, Reliability, oxide breakdown, cascade E-class, output power, low power consumption
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  • 在本論文中,主要分析無線射頻收發器中個別子電路設計及其可靠性,包括功率放大器、壓控震盪器與混頻器,我們利用各電路相關工作電壓與信號輸入功率大小來進行長時間的電性應力加壓,並以電路特性退化的程度進一步分析其學理上元件的退化與其來源。
    而在E類功率放大器的可靠度部分,其利用基於第一級為驅動級來推動第二級的串疊組態,工作頻率為5.2GHz,並以TSMC CMOS 0.18µm 1P6M 之製程設計。由於放大器主要的工作原理是在大信號的操作條件下,而在高功率的RF信號輸入下,加上本身高增益的放大,其串疊電晶體所承受的汲極應力電壓將會比下方的主要電晶體大很多。而其主要的可靠性分析是當汲源極電壓與閘源極電壓在隨時間切換下,電晶體所承受的高比例電壓上升下降而引起的熱載子效應,導致電路性能衰退。隨著時間的電性應力測試與性能的衰退所得到的數據,再進一步利用TCAD軟體進行驗證與比對其現象。
    關於TSMC CMOS 0.18µm 1P6M 製程設計的電源再利用技術結構之震盪器,我們利用n 通道與p 通道金氧半場效電晶體的偏壓特性,形成單一回路的震盪器結構,此結構具有低功率消耗的特性。再者基於P-MOS較低雜訊的特性,偏壓成可變電容使用,再搭配電感來形成共振器以提供工作頻率的選擇。取得最佳的VDD電壓條件以構成低相位雜訊低功率消耗之壓控振盪器。而此電路中的n 通道與p 通道金氧半場效電晶體組成之電路會有負偏壓溫度不穩定性(NBTI:Negative Bias Temperature Instability)的問題存在,在此章中我們會提出其效應對電路的影響,並討論熱載子效應所導致的相位雜訊衰退、臨界電壓變大、及轉移電導下降等現象。
    而最後一部分,介紹了毫米波頻段之混波器,此處利用TSMC CMOS 65nm 1P6M 製程設計之混波器,其64~75GHz頻段之轉換增益皆大於-5dB,最大輸出轉換增益為-0.96dB。此混波器使用Double balanced架構並內建Balun 於本地與射頻端,這種作法可以減少外部儀器跟配件的使用從而簡化實驗的變因,由於IF的量測配件相當齊全且特性佳,我們保留了差動對的形式,以方便後續實驗規劃。我們在毫米波的頻率下進行動態應力可靠性實驗,在長時間的應力下,電路因熱載子效應而退化,使得n通道金氧半場效電晶體臨界電壓上升,其閘極漏電流也隨著在長時間閘汲極電壓應力而增加。最後我們也利用實際的單顆之n通道金氧半場效電晶體在不同應力條件,來解釋電路長時間的應力下因為熱載子、汲極內部高電場所帶來的衰退現象。


    For this dissertation, the radio frequency (RF) and millimeter wave circuits of transceivers were considered in order to analyze reliability issues with regard to the complementary-metal–oxide–semiconductor (CMOS) process.
    Three circuits were considered: a power amplifier (PA), voltage control oscillator (VCO), and mixer. In a stress experiment, the operation voltage was varied for the stress source, and the degradation of the circuit was monitored to analyze phenomena that degraded the device and circuit performance. The stress source conditions were controlled by the input power and voltage of instruments that were biased towards the gate and drain of the CMOS device on the circuits. In reliability experiments, acceptable values for the stress source were applied to the circuits to induce long-term stress.
    In the PA circuit topology, stage 1 was a driver stage, and stage 2 was a cascode structure. The circuit operation frequency was 5.2 GHz for a TSMC CMOS 0.18 µm 1P6M process. A cascode class-E PA was designed for fabrication because the amplifier was operated under high input power conditions. The input power, gain, gate–source voltages, and drain–source voltages had large values when switching during the transient state. Thus, the cascode transistor could suffer from the hot-electron effect and the degradation of the circuit performance. The experimental results were compared with those of a technology computer-aided design (TCAD) simulation to examine the reasons for the degradation of the circuit performance.
    The design and reliability of a CMOS current-reuse LC-loaded VCO based on the TSMC CMOS 0.18 µm 1P6M process were considered. The circuit comprised an n-channel MOS and p-channel MOS cross pair with a single current path oscillator structure, which allowed it to have low power consumption. The varactor component of the LC resonator was designed with a P-MOS device having low noise characteristics. The operation frequency was determined by the LC resonator, and a suitable VDD voltage led to low power consumption and low phase noise for the VCO. The negative-bias temperature instability (NBTI) affected the current for the reused VCO, which consisted of p-channel transistors. Previous studies had not examined the circuit topology experimentally, which provided motivation for this dissertation. Hot carrier issues for the degradation of the phase noise, transconductor, and threshold were considered.
    Finally, a millimeter wave mixer was considered for the TSMC CMOS 65 nm 1P6M process at conversion gains of larger than -5 dB. The coverage frequency was from 64 GHz to 75 GHz, and the maximum conversion gain was -0.96 dB. Two built-in Marchand baluns were used to convert the LO and RF port from single to differential. This can simplify the external passive parts and instruments used for the millimeter-wave band. The IF port provided excellent performance characteristic for the external passive parts and instruments. The IF port retained differential characteristics, which can be advantageous for circuit measurement during experiments. In this experiment, the mixer was operated at millimeter wave frequency range. Long-term and dynamic stresses on the n-channel metal–oxide–semiconductor field-effect transistor (MOSFET) device resulted in the hot carrier effect, which degraded the mixer performance. This increased the threshold voltage and gate leakage current and decreased the drain current. A stress measurement experiment was performed under different stress conditions for the n-channel MOSFET. The results showed how mechanisms such as a hot carrier and high electric field influenced the device characteristics under long-term stress.

    Table of contents Abstract (Chinese) i Abstract (English) iii Acknowledgements Table of Contents v Figures Captions vii Tables Captions ix Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Dissertation Organization 2 Chapter 2 Design of Measurement Environment and Stress Measurement Methods 5 2.1 Design of Measurement Environment 5 2.2 Design of Stress Measurement Environment for PA 8 2.3 Design of Stress Measurement Environment for VCO 12 2.4 Design of Stress Measurement Environment for Mixer 14 Chapter 3 Experimental Verification of RF Stress Effect on Cascode Class-E PA Performance and Reliability 18 3.1 Introduction 18 3.2 Design of a Cascode Class-E PA 20 3.3 RF Stress Experiments 24 3.4 Physical Insight Through The Mixed-Mode Device And Circuit Simulation 28 3.5 Conclusion 33 Chapter 4 RF Stress Effects on CMOS LC-loaded VCO Reliability Evaluated by Experiments 35 4.1 Introduction 35 4.2 Design of the LC loaded-VCO 37 4.3 RF Stress Experiments 41 4.4 Conclusion 48 Chapter 5 Reliability Evaluation of 65nm Double Balanced Mixer by Experiment 49 5.1 Introduction 49 5.2 Circuit Design 50 5.3 Mixer Performance by Experiments 53 5.4 Stress Experimental Data 57 5.4.1 Transistor Stress Measurement 59 5.4.2 Mixer Stress Measurement Data 62 5.5 Conclusion 65 Chapter 6 Conclusion 67 Reference 71 Publication List 79

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