由於製程技術急速成長與晶片製造上的問題，多元件間距限制應運而生。比如，我們可以利用多元件間距限制來處理次10奈米節點下的接腳可達性問題。本論文研究考量了通用的多元件間距限制下的混合元件細部擺置問題。一個直覺上的二元件方法是將每個多元件間距限制切割成多個二元件間距限制，但這樣會造成總元件移動量遠超過需求。因此，欲處理此問題，我們提出一個實際的多元件方法。首先，我們提供了3種方法以分析布局與限制以藉此判斷哪些元件對是最容易拆開。再者，我們應用了一個基於單列動態規劃的方法於各列上，此方法稱作列內移動(IRM)，以解決絕大部分的限制違反並最小化總元件移動量或是總線長增加量。有了元件虛擬化(cell virtualization)技術與可移動區域計算(movable region computation)技術，IRM可以被延伸以處理混合元件高度的設計，且無須變更原本動態規劃的方法，只需在成本預估上做一點微小的變更即可達成。最後，我們提供了兩種方法來做全局移動(GM)，並保持總元件移動量為最小。眾多的實驗結果顯示與支持我們的多元件方法相當有效率與有效果。

Multi-cell spacing constraints arise due to aggressive technology scaling and manufacturing issues. For example, we can incorporate multi-cell spacing constraints to tackle pin accessibility problem in sub-10nm nodes. This thesis studies mixed-cell-height detailed placement considering generic multi-cell spacing constraints. A naive 2-cell method is to model each multi-cell spacing constraint as a set of 2-cell spacing constraints, but the resulting total cell displacement would be much larger than necessary. Thus, we aim to tackle this problem and propose a practical multi-cell method. First, we present 3 ways to analyze the initial layout to determine which cell pair in each multi-cell spacing constraint is the easiest to break apart. Secondly, we apply a single-row dynamic programming (SRDP)-based method one row at a time, called Intra-Row Move (IRM), to resolve a majority of violations while minimizing the total cell displacement or wirelength increase. With cell virtualization and movable region computation techniques, our IRM can be easily extended to handle mixed-cell-height designs with only a slight modification of the cost computation in the SRDP method. Finally, we present 2 ways to perform Global Move (GM) to resolve the remaining violations while minimizing the total cell displacement. Versatile experimental results prove and support the efficacy and effectiveness of our approach.

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