覆晶封裝（Flip chip）的封裝方式乃是現今廣泛應用於消費型電子產品的封裝技術，其封裝之體積較小，能節省最終產品所需之空間。在製程中所需的關鍵技術是所謂的晶圓凸塊（Bumping process），即是在晶圓代工廠產出後的整片晶圓上直接在導通開孔（IO pad）上電鍍上做為金屬傳導的金屬凸塊，過去大多為高鉛或是錫鉛的合金金屬，隨著環保的要求與意識，現在大多將產品轉為錫銀合金。
由於消費性電子產品的世代更新速度快速，開發過程最重視的即是如何增進產品量產以及上市的效率。然而，在晶圓凸塊的新產品導入時，需要耗費大量時間與控片測試（Dummy test）來找尋最佳電鍍參數（Parameter fine tune），過去實務上大多憑藉工程師的經驗法則來做為新產品開發時參數選訂的依據，需浪費大量控片測試時間與成本。本研究利用倒傳遞類神經網路（Back propagation neural network, BPN）來建立預測模式，經以過去實際量產之數據進行驗證，本研究所建立之預測模型可有效降低量產前所需之測試時間與成本。

Flip chip process is a mature assembly techniques used in the packaging industry for consumer products today. The IC product size of this assembly technology is quite small that can reduce the device volume. The key technique in the flip chip process is bumping process which is generated the solder bump on IO pad of the wafer via electrochemical plating. In the past, the composition of the metal was high-lead or lead-solder eutectic metallization. Today, most firms follow with environmental ROHS regulations; majority customers required their product to adopt silver soldering material in recent years.
Electrical device’s life cycle is much shorter nowadays, product development timeline become a challenge task for quality yield and product launch timing. Firms spent a lot of time and dummy test for parameter fine tune during the bumping new-product-introduce stage. In the past, engineer searched for historical data to set the parameter but it needs a long time and with high cost. In this study, we provide an approach which demonstrate a back-propagation network to construct a prediction model by using the historical data and the performance by data and actual in-line enhancement to verify the benefit of time and cost saving by this method.

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