研究生: |
郭皇志 Huang-Chih Kuo |
---|---|
論文名稱: |
針對高解析度H.264/MPEG-4 Part10 AVC編碼中幅內與幅間模式決策器的高效率超大型積體電路架構 Efficient VLSI Architectures for Inter and Intra Mode Decision in High Resolution H.264/MPEG-4 Part10 AVC Encoding |
指導教授: |
林永隆
Youn-Long Lin |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 資訊工程學系 Computer Science |
論文出版年: | 2006 |
畢業學年度: | 94 |
語文別: | 英文 |
論文頁數: | 33 |
中文關鍵詞: | H.264先進影像壓縮技術 、幅內模式選擇器 、幅間模式選擇器 |
相關次數: | 點閱:2 下載:0 |
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我們針對高解析度H.264先進影像壓縮技術中的幅內與幅間模式選擇器提出了高效能的硬體架構。我們的方法和H.264先進影像壓縮技術的參考軟體有著一樣的影像壓縮品質。在我們的幅內模式選擇器中,我們採用了創新的資源共享機制來支援多幅參考。使用臺灣積體電路製造股份有限公司的0.13微米製程技術來合成我們的設計,在100萬赫茲的工作頻率下,我們的幅內模式選擇器使用了約28000個邏輯閘而幅間模式選擇器使用了約24000個邏輯閘。在25萬赫茲的工作頻率下,我們的幅內模式選擇器和幅間模式選擇器都能每秒壓縮30張解析度為720p HD (1280x720) 的影像畫面。我們並使用一個多媒體系統晶片平臺來將我們的模式選擇器整合到一個支援H.264先進影像壓縮技術主要規格的壓縮系統中。
We propose two efficient hardware architectures for inter and intra mode decision, respectively, in high resolution H.264/AVC encoding. Our approach delivers almost the same video quality as the H.264/AVC reference software does. Our inter mode decision architecture employs a novel resource sharing scheme to support multiple reference frames. Synthesized using a TSMC .13μm CMOS cell library, our inter mode decision unit and intra mode decision unit take 28k and 25k gates, respectively, for 100 MHz performance. Both units can encode 720p HD (1280x720) video at 30 frames per second when running at a 25-MHz FPGA platform. We have integrated the proposed mode decision units into an H.264/AVC main profile encoder system using a multimedia SOC platform.
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