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研究生: 郭皇志
Huang-Chih Kuo
論文名稱: 針對高解析度H.264/MPEG-4 Part10 AVC編碼中幅內與幅間模式決策器的高效率超大型積體電路架構
Efficient VLSI Architectures for Inter and Intra Mode Decision in High Resolution H.264/MPEG-4 Part10 AVC Encoding
指導教授: 林永隆
Youn-Long Lin
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年: 2006
畢業學年度: 94
語文別: 英文
論文頁數: 33
中文關鍵詞: H.264先進影像壓縮技術幅內模式選擇器幅間模式選擇器
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  • 我們針對高解析度H.264先進影像壓縮技術中的幅內與幅間模式選擇器提出了高效能的硬體架構。我們的方法和H.264先進影像壓縮技術的參考軟體有著一樣的影像壓縮品質。在我們的幅內模式選擇器中,我們採用了創新的資源共享機制來支援多幅參考。使用臺灣積體電路製造股份有限公司的0.13微米製程技術來合成我們的設計,在100萬赫茲的工作頻率下,我們的幅內模式選擇器使用了約28000個邏輯閘而幅間模式選擇器使用了約24000個邏輯閘。在25萬赫茲的工作頻率下,我們的幅內模式選擇器和幅間模式選擇器都能每秒壓縮30張解析度為720p HD (1280x720) 的影像畫面。我們並使用一個多媒體系統晶片平臺來將我們的模式選擇器整合到一個支援H.264先進影像壓縮技術主要規格的壓縮系統中。


    We propose two efficient hardware architectures for inter and intra mode decision, respectively, in high resolution H.264/AVC encoding. Our approach delivers almost the same video quality as the H.264/AVC reference software does. Our inter mode decision architecture employs a novel resource sharing scheme to support multiple reference frames. Synthesized using a TSMC .13μm CMOS cell library, our inter mode decision unit and intra mode decision unit take 28k and 25k gates, respectively, for 100 MHz performance. Both units can encode 720p HD (1280x720) video at 30 frames per second when running at a 25-MHz FPGA platform. We have integrated the proposed mode decision units into an H.264/AVC main profile encoder system using a multimedia SOC platform.

    Contents Abstract I Contents II List of Figures VI List of Tables V Chapter 1 1 Introduction 1 Chapter 2 7 Mode Decision Algorithm and Encoding Flow 7 2.1 Mode Decision Algorithms 7 2.1.1 Rate-Distortion Optimized Mode Decision 8 2.1.2 Low Complexity Mode Decision 9 2.2 Encoding Flow of Inter Mode Decision 10 2.3 Encoding Flow of Intra Mode Decision 11 Chapter 3 14 Previous Work 14 3.1 Fast Mode Decision Algorithms 14 3.2 Hardware Implementation 15 Chapter 4 17 Proposed Approach 17 4.1 Modified Cost Function 17 4.2 Proposed Inter Mode Decision Architecture 18 4.2.1 Block diagram of proposed inter mode decision 18 4.2.2 Timing analysis of proposed inter mode decision 20 4.3 Proposed Intra Mode Decision Architecture 21 4.3.1 Block diagram of proposed intra mode decision 21 4.3.2 Timing analysis of proposed intra mode decision 23 Chapter 5 25 Experimental Results 25 5.1 System Design Flow 25 5.2 IP Qualification 26 5.3 FPGA Synthesis Result 26 5.4 Video Quality 27 5.5 Architecture Comparison 29 Chapter 6 31 Conclusion and Future Work 31 Bibliography 32

    [1] T. C. Chen, Y. W. Huang, L.G. Chen, “Fully Utilized and Reusable Architecture for Fractional Motion Estimation of H.264/AVC,” IEEE International Conference on Acoustics, Speech, and Signal Processing, vol. 5, pp. 9-12, May 2004.
    [2] Y. W. Huang, B. Y. Hsieh, T. C. Chen, and L. G. Chen, “Analysis, Fast Algorithm, and VLSI Architecture Design for H.264/AVC Intra Frame Coder,” IEEE Transactions on Circuit and Systems for Video Technology, vol. 15, pp. 378-401, March 2005.
    [3] Y. H. Kim, J. W. Yoo, S. W. Lee, J. Shin, J. Paik, H. K. Jung, “Adaptive Mode Decision for H.264 encoder,” 16th IEE Electronic Letters, vol. 40, pp. 1172- 1173, September 2004
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    [6] F. Pan, X. Lin, S. Rahardja, K. P. Lim, Z.G. Li, D. Wu, S. Wu, “Fast mode decision algorithm for intra prediction in H.264/AVC video coding,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, pp.813-822, July 2005
    [7] W. K. Pratt, “Digital Image Processing”, John Wiley & Sons, 1978
    [8] G. J. Sullivan, T. Wiegand, “Rate-Distortion Optimization for Video Compression,” IEEE Signal Processing Magazine, vol. 15, pp. 74-90, November 1998.
    [9] Joint Video Team, “Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec. H.264|ISO/IEC 4496-10 AVC),” JVT-G050, May 2003
    [10] T. Wiegand, B. Girod, “Lagrange Multiplier Selection in Hybrid Video Coder Control,” IEEE International Conference on Image Processing, vol. 3, pp. 542-545, October 2001
    [11] T. Wiegand, H. Schwarz, A. Joch, F. Kossentini, G. J. Sullivan, “Rate-Constrained Coder Control and Comparison of Video Coding Standards,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, pp.688-703, July 2003.
    [12] Reference Software JM 9.0, Joint Video Team,
    http://iphome.hhi.de/suehring/tml/download/old_jm/
    [13] nLint, Novas Software,
    http://www.novas.com/Solutions/nLint/
    [14] Verification Navigator, TransEDA
    http://www.transeda.com/index.php?option=com_content&task=view&id=88&Itemid=273
    [15] Stratix II, Altrea Corporation
    http://www.altera.com/products/devices/stratix2/st2-index.jsp
    [16] Synplify Pro, Synplicity
    http://www.synplicity.com/products/synplifypro/index.html
    [17] QuartusII, Altera Corporation
    http://www.altera.com/products/software/products/quartus2/qts-index.html

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