本研究利用錫作為摻雜物與催化劑，於低溫(≦400 °C)下成長含錫摻雜之銅金屬奈米線，其低電阻及高電流密度的特性，可做為未來積體電路內連線之應用。並藉由調變基板錫膜厚度、試片前處理、反應溫度、反應壓力及前驅物比例等成長條件，來增加奈米線成長的密度。
本研究成功利用銅粉與氯化亞錫粉末作為前驅物，以化學氣相沉積的方式，將前驅物沉積至基板而生成奈米線，並透過SEM、TEM等分析儀器確認奈米線之形貌、結晶性與其組成成分。此外，同時對前驅物反應後的產物作XRD分析，提出奈米線的成長機制，銅錫奈米線主要經由VLS成長機制生成。為使奈米線日後能應用於內連線結構內，本研究也嘗試將奈米線製備於內連線連接孔(via)內，並成功將奈米線於連接孔內成長。
而在電性分析方面，含錫摻雜之銅金屬奈米線具有低電阻(3 μΩ-cm)及高承載電流密度(3.16×107 A/cm2)，此電阻亦為目前所發表相關銅基奈米線文獻中最低電阻率，顯示錫摻雜之銅金屬奈米線極有潛力成為內連線應用之材料。

This work presents the synthesis of tin-doped copper nanowires by introducing Sn not only as a catalyst to enhance the reduction of Cu but also as a dopant to grow the tin-doped copper NWs at low temperature (≦ 400 °C). It is believed that tin-doped copper NWs are good candidates for future CMOS interconnect applications because of their good electrical properties. In addition, this work is also focused on the optimization of the thickness of Sn, pretreatment of substrates, temperature, pressure, and the ratio of precursor compositions to obtain the high-density nanowires.
The tin-doped copper nanowires (25 μm in length and 50–200 nm in diameter) have been successfully synthesized by chemical vapor deposition (CVD) using the Cu and SnCl2 powders as precursors. The morphology and crystalline structure of the tin-doped copper nanowires were characterized by scanning electron microscopy (SEM) and high resolution transmission electron microscopy (HR-TEM), respectively. Additionally, the mechanism of Cu(Sn) nanowires formation is proposed to be vapor–liquid-solid (VLS) reaction growth. Finally, Cu(Sn) nanowires (NWs) were also synthesized in the via hole to confirm the ability for interconnect application.
In electrical properties part, the tin-doped copper NWs exhibit low resistivity (3 μΩ-cm), which is the lowest value reported so far, and maximum current density (3.16×107 A/cm2). It indicates that tin-doped copper NWs exhibit great potential to be future interconnect materials.

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