如今，快閃記憶體已廣泛地應用於可攜式電子產品上，如智慧型手機與平板電腦。傳統浮動式閘極快閃記憶體因為其結構與可靠度問題，使得元件已無法滿足微縮發展的趨勢，因此利用電荷陷阱式快閃記憶體取代浮動閘極結構元件已是未來發展的趨勢。然而當傳統SONOS記憶體元件發展到次微米以下，就無法再以降低穿隧氧化層厚度來提升元件的操作效率。所以有許多改良的SONOS元件也因此而發展出來，例如能帶工程SONOS元件。利用非常薄的薄膜堆疊的穿隧氧化層，在寫入與抹除時的高電場下，電荷穿隧距離會因部分穿隧能障消失而有效降低。
　　在本篇論文中，我們利用此概念因而設計了（低溫）多氮型氮化矽/氧化矽堆疊的穿隧氧化層作為SONOS元件的穿隧氧化層。此外，由於奈米線通道結構能提高閘極對通道的控制能力，並能有效地降低臨界電壓（threshold voltage）、漏電流等，且基本電性都較一般標準結構的薄膜電晶體好，所以我們也進一步結合了利用側壁空間層的製作方式所形成的奈米線通道薄膜電晶體。由於奈米線通道結構的SONOS元件，在元件操作時有明顯的EBT（Electron back tunneling）現象發生，所以我們也把高介電係數材料以及高功函數金屬應用在電荷阻擋層與閘極上，並且對基本電特性、寫入/抹除速度、可靠度做詳細的分析探討。
　　由實驗結果發現，（低溫）多氮型氮化矽/氧化矽堆疊的穿隧氧化層能有效的提升寫抹速度，但在資料保存性上較差。使用奈米線通道結構的SONOS元件，由於奈米線通道有較小的曲率半徑，使得有較快的寫入與抹除速度。多氮型氮化矽/氧化矽堆疊的穿隧氧化層也能有效的提升寫抹除速度，但在抹除時卻有很明顯的EBT現象發生。資料保存性上也較差些。搭配高介電材料的阻擋層與高功函數金屬閘極的奈米線通道的元件，元件操作時已經沒有EBT發生，而且多氮型氮化矽/氧化矽堆疊的穿隧氧化層也能有效的提升寫入與抹除速度，資料保存性上仍較差些。但在經過一千次擦寫後的電荷保持力卻以堆疊式的穿隧氧化層較好。

Chapter 1
[1.1] Min She, “Semiconductor Flash Memory Scaling”, 2003.
[1.2] M. White, D. Adams, and J. Bu, “On the go with SONOS,” IEEE Circuits and Devices Magazine,, vol. 16, no. 4, Jul 2000, pp. 22 –31.
[1.3] M. White, Y. Yang, A. Purwar, and M. French, “A low voltage SONOS nonvolatile semiconductor memory technology,” in Nonvolatile Memory Technology Conference, 1996., Sixth Biennial IEEE International, Jun 1996, pp. 52 –57.
[1.4] J. Bu and M. White, “Retention reliability enhanced SONOS NVSM with scaled programming voltage,” in Aerospace Conference Proceedings, 2002. IEEE, vol. 5, 2002, pp. 5–2383 – 5–2390 vol.5.
[1.5] K. San, C. Kaya, and T. Ma, “Effects of erase source bias on flash EPROM device reliability,” Electron Devices, IEEE Transactions on, vol. 42, no. 1, pp. 150 –159, Jan 1995.
[1.6] K. Kahng and S. Sze, “A floating gate and its application to memory devices,” Electron Devices, IEEE Transactions on, vol. 14, no. 9, p. 629, Sep 1967.
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[1.10] T. Sugizaki, M. Kobayashi, M. Ishidao, H. Minakata, M. Yamaguchi, Y. Tamura, Y. Sugiyama, T. Nakanishi, and H. Tanaka, “Novel multi-bit SNOS type flash memory using a high-k charge trapping layer,” in VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on, June 2003, pp. 27 – 28.
[1.11] Y.-N. Tan, W.-K. Chim, B. J. Cho, and W.-K. Choi, “Over-erase phenomenon in SONOS-type flash memory and its minimization using a hafnium oxide charge storage layer,” Electron Devices, IEEE Transactions on, vol. 51, no. 7, pp. 1143 – 1147, July 2004.
[1.12] Y. N. Tan, W. Chim, W. K. Choi, M. S. Joo, and B. J. Cho, “Hafnium aluminum oxide as charge storage and blocking-oxide layers in SONOS-type nonvolatile memory for high-speed operation,” Electron Devices, IEEE Transactions on, vol. 53, no. 4, pp. 654 – 662, April 2006.
[1.13] C.-C. Wang, K.-S. Chang-Liao, C.-Y. Lu, and T.-K. Wang, “Enhanced band-to-band-tunneling-induced hot-electron injection in p-channel flash by band-gap offset modification,” Electron Device Letters, IEEE, vol. 27, no. 9, pp. 749 –751, Sept. 2006.
[1.14] H.-T. Lue, S.-C. Lai, T.-H. Hsu, Y.-H. Hsiao, P.-Y. Du, S.-Y. Wang, K.-Y. Hsieh, R. Liu, and C.-Y. Lu, “A critical review of charge-trapping nand flash devices,” in Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on, oct. 2008, pp. 807 –810.
[1.15] T.-H. Hsu, H.-T. Lue, Y.-C. King, Y.-H. Hsiao, S.-C. Lai, K.-Y. Hsieh, R. Liu, and C.-Y. Lu, “Physical model of field enhancement and edge effects of FINFET charge-trapping NAND flash devices,” IEEE Trans. Electron Devices, vol. 56, no. 6, pp. 1235 –1242, June 2009.
[1.16] P.-C. Huang, L.-A. Chen, and J.-T. Sheu, “Electric-field enhancement of a gate-all-around nanowire thin-film transistor memory,” IEEE Electron Device Lett., vol. 31, no. 3, pp. 216 –218, March 2010.
[1.17] S.-C. Chen, T.-C. Chang, P.-T. Liu, Y.-C. Wu, C.-C. Ko, S. Yang, L.-W. Feng, S. M. Sze, C.-Y. Chang, and C.-H. Lien, “Pi-shape gate Polycrystalline silicon thin-film transistor for nonvolatile memory applications,” Appl. Phys. Lett., vol. 91, no. 21, pp. 213101 – 213101–3, Nov 2007.
[1.18] L.-J. Chen, Y.-C. Wu, J.-H. Chiang, M.-F. Hung, C.-W. Chang, and P.-W. Su, “Comprehensive study of pi-gate nanowires poly-Si TFT nonvolatile memory with an HfO charge trapping layer,” IEEE Trans. Nanotechnol., vol. 10, no. 2, pp. 260 –265, March 2011.
[1.19] G.-Q. Lo, C. Zhu, J. Fu, D.-L. Kwong, and N. Singh, “Integration of high- k dielectrics and metal gate on gate-all-around Si-nanowire-based architecture for high-speed nonvolatile charge-trapping memory,” Electron Device Letters, IEEE, vol. 30, no. 6, pp. 662 –664, June 2009

Chapter2
[2.1] S. Tam, P.-K. Ko, and C. Hu, “Lucky-electron model of channel hot- electron injection in MOSFET’s,” Electron Devices, IEEE Transactions on, vol. 31, no. 9, pp. 1116 – 1125, Sep 1984.
[2.2] J. Bu and M. White, “Retention reliability enhanced SONOS NVSM with scaled programming voltage,” in Aerospace Conference Proceedings, 2002. IEEE, vol. 5, 2002, pp. 5–2383 – 5–2390 vol.5.
[2.3] W. Tsai, N. Zous, C. Liu, C. Liu, C. Chen, T. Wang, S. Pan, C.-Y. Lu, and S. Gu, “Data retention behavior of a SONOS type two-bit storage flash memory cell,” in Electron Devices Meeting, 2001. IEDM ’01. Technical Digest. International, 2001, pp. 32.6.1 –32.6.4.
[2.4] K. San, C. Kaya, and T. Ma, “Effects of erase source bias on flash EPROM device reliability,” Electron Devices, IEEE Transactions on, vol. 42, no. 1, pp. 150 –159, Jan 1995.
[2.5] T. Sugizaki, M. Kobayashi, M. Ishidao, H. Minakata, M. Yamaguchi, Y. Tamura, Y. Sugiyama, T. Nakanishi, and H. Tanaka, “Novel multi-bit SNOS type flash memory using a high-k charge trapping layer,” in VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on, June 2003, pp. 27 – 28.
[2.6] Y.-N. Tan, W.-K. Chim, B. J. Cho, and W.-K. Choi, “Over-erase phenomenon in SONOS-type flash memory and its minimization using a hafnium oxide charge storage layer,” Electron Devices, IEEE Transactions on, vol. 51, no. 7, pp. 1143 – 1147, July 2004.
[2.7] S. Mahapatra, S. Shukuri, and J. Bude, “CHISEL flash EEPROM – Part I: Performance and scaling,” IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 49, no. 7, pp. 1296–1301, Jul 2002.

Chapter 3
[3.1] J.-G. Yun, I. L. H. Park, S. Cho, J. H. Lee, D.-H. Kim, G. S. Lee, Y. Kim, J.-D. Lee, and B.-G. Park, “Formation of Si-rich silicon nitride with low deposition rate by using LPCVD for nanoscale non-volatile-memory application,” JOURNAL OF THE KOREAN PHYSICAL SOCI-ETY, vol. 51, no. 3, pp. S229–S233, DEC 2007, 14th Korean Conference on Semiconductors, Cheju Isl, SOUTH KOREA, FEB 08-09, 2007
[3.2] T.-S. Chen, K.-H. Wu, H. Chung, and C.-H. Kao, “Performance improvement of SONOS memory by bandgap engineering of charge-trapping layer,” Electron Device Letters, IEEE, vol. 25, no. 4, pp. 205 – 207, April 2004.
[3.3] H.-T. Lue, S.-C. Lai, T.-H. Hsu, Y.-H. Hsiao, P.-Y. Du, S.-Y. Wang, K.-Y. Hsieh, R. Liu, and C.-Y. Lu, “A critical review of charge-trapping nand flash devices,” in Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on, oct. 2008, pp. 807 –810.
[3.4] Y. Wang, D. Gao, W. Hwang, C. Shen, G. Zhang, G. Samudra, Y. Yeo, and W. Yoo, “Fast erasing and highly reliable MONOS type memory with hfo2 high-k trapping layer and Si3N4/SiO2 tunneling stack,” in Electron Devices Meeting, 2006. IEDM ’06. International, Dec. 2006, pp. 1 –4.
[3.5] P.-H. Tsai, K.-S. Chang-Liao, T.-Y. Wu, T.-K. Wang, P.-J. Tzeng, C.-H. Lin, L.-S. Lee, and M.-J. Tsai, “Novel SONOS-type nonvolatile memory device with stacked tunneling and charge-trapping layers,” in Semiconductor Device Research Symposium, 2007 International, Dec. 2007, pp.1 –2.
[3.6] D. Gilmer, N. Goel, H. Park, C. Park, S. Verma, G. Bersuker, P. Lysaght, H.-H. Tseng, P. Kirsch, K. Saraswat, and R. Jammy, “Engineering the complete MANOS-type NVM stack for best in class retention performance,” in Electron Devices Meeting (IEDM), 2009 IEEE International, Dec. 2009, pp. 1 –4.
[3.7] T. H. Kim, I. H. Park, J. D. Lee, H. C. Shin, and B.-G. Park, “Electron trap density distribution of Si-rich silicon nitride extracted using the modified negative charge decay model of silicon-oxide-nitride-oxide-silicon structure at elevated temperatures,” Applied Physics Letters, vol. 89, no. 6, pp. 063 508 –063 508–3, Aug 2006.

Chapter 4
[4.1] H. Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, M. Kito, Y. Fukuzumi, M. Sato, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi, and A. Nitayama, “Bit cost scalable technology with punch and plug process for ultra high density flash memory,” in VLSI Technology, 2007 IEEE Symposium on, June 2007, pp. 14 –15.
[4.2] J. Jang, H.-S. Kim, W. Cho, H. Cho, J. Kim, S. I. Shim, Y. Jang, J.-H. Jeong, B.-K. Son, D. W. Kim, Kihyun, J.-J. Shim, J. S. Lim, K.-H. Kim, S. Y. Yi, J.-Y. Lim, D. Chung, H.-C. Moon, S. Hwang, J.-W. Lee, Y.-H. Son, U.-I. Chung, and W.-S. Lee, “Vertical cell array using TCAT(terabit cell array transistor) technology for ultra-high density NAND flash memory,” in VLSI Symp. Tech. Dig., 2009, pp. 192 –193.
[4.3] H.-T. Lue, T.-H. Hsu, Y.-H. Hsiao, S. Hong, M. Wu, F. Hsu, N. Lien, S.-Y. Wang, J.-Y. Hsieh, L.-W. Yang, T. Yang, K.-C. Chen, K.-Y. Hsieh, and C.-Y. Lu, “A highly scalable 8-layer 3d vertical-gate (VG) TFT NAND flash using junction-free buried channel BE-SONOS device,” in VLSI Symp. Tech. Dig., 2010, pp. 131 –132.
[4.4] P.-C. Huang, L.-A. Chen, and J.-T. Sheu, “Electric-field enhancement of a gate-all-around nanowire thin-film transistor memory,” IEEE Electron Device Lett., vol. 31, no. 3, pp. 216 –218, March 2010.
[4.5] T.-H. Hsu, H.-T. Lue, Y.-C. King, Y.-H. Hsiao, S.-C. Lai, K.-Y. Hsieh, R. Liu, and C.-Y. Lu, “Physical model of field enhancement and edge effects of FINFET charge-trapping NAND flash devices,” IEEE Trans. Electron Devices, vol. 56, no. 6, pp. 1235 –1242, June 2009.
[4.6] S.-C. Chen, T.-C. Chang, P.-T. Liu, Y.-C. Wu, C.-C. Ko, S. Yang, L.-W. Feng, S. M. Sze, C.-Y. Chang, and C.-H. Lien, “Pi-shape gate polycrystalline silicon thin-film transistor for nonvolatile memory applications,” Applied Physics Letters, vol. 91, no. 21, pp. 213 101 –213 101–3, Nov 2007.
[4.7] G.-Q. Lo, C. Zhu, J. Fu, D.-L. Kwong, and N. Singh, “Integration of high- k dielectrics and metal gate on gate-all-around Si-nanowire-based architecture for high-speed nonvolatile charge-trapping memory,” Electron Device Letters, IEEE, vol. 30, no. 6, pp. 662 –664, June 2009
[4.8] P.-T. Liu, C. S. Huang, and C. W. Chen, “Enhanced planar poly-Si TFT EEPROM cell for system on panel applications,” ELECTROCHEMICAL AND SOLID STATE LETTERS, vol. 10, no. 8, pp. J89–J91, 2007.
[4.9] H.-H. Hsu, T.-W. Liu, C.-D. Lin, C. Kuo-Jung, T.-Y. Huang, and H.-C. Lin, “Tri-gated poly-Si nanowire SONOS devices,” in VLSI Technology,Systems, and Applications, 2009. VLSI-TSA ’09. International Symposium on, April 2009, pp. 148 –149.
[4.10] T.-C. Liao, S.-K. Chen, M. Yu, C.-Y. Wu, T.-K. Kang, F.-T. Chien, Y.-T. Liu, C.-M. Lin, and H.-C. Cheng, “A novel LTPS-TFT-based charge-trapping memory device with field-enhanced nanowire structure,” in Electron Devices Meeting (IEDM), 2009 IEEE International, Dec. 2009, pp. 1 –4.

Chapter 5
[5.1] Y. N. Tan, W. Chim, W. K. Choi, M. S. Joo, and B. J. Cho, “Hafnium aluminum oxide as charge storage and blocking-oxide layers in SONOS- type nonvolatile memory for high-speed operation,” Electron Devices, IEEE Transactions on, vol. 53, no. 4, pp. 654 – 662, April 2006.
[5.2] C.-C. Wang, K.-S. Chang-Liao, C.-Y. Lu, and T.-K. Wang, “Enhanced band-to-band-tunneling-induced hot-electron injection in p-channel flash by band-gap offset modification,” Electron Device Letters, IEEE, vol. 27, no. 9, pp. 749 –751, Sept. 2006.
[5.3] Y.-C. Wu, C.-Y. Chang, T.-C. Chang, P.-T. Liu, C.-S. Chen, C.-H. Tu, H.-W. Zan, Y.-H. Tai, and S. M. Sze, “High performance and high reliability polysilicon thin-film transistors with multiple nano-wire channels,” in Electron Devices Meeting, 2004. IEDM Technical Digest.
IEEE International, Dec. 2004, pp. 777 – 780.
[5.4] J. Fu, Y. Jiang, N. Singh, C. Zhu, G. Lo, and D. Kwong, “Polycrystalline Si nanowire SONOS nonvolatile memory cell fabricated on a gate-all-around (GAA) channel architecture,” Electron Device Letters, IEEE, vol. 30, no. 3, pp. 246 –249, March 2009.
[5.5] P.-C. Huang, L.-A. Chen, and J.-T. Sheu, “Electric-field enhancement of a gate-all-around nanowire thin-film transistor memory,” IEEE Electron Device Lett., vol. 31, no. 3, pp. 216 –218, March 2010.
[5.6] C.-Y. Wu, Y.-T. Liu, T.-C. Liao, M. Yu, and H.-C. Cheng, “Novel dielectric-engineered trapping-charge poly-Si-TFT memory with a TiN-Alumina-Nitride-vacuum-Silicon structure,” IEEE Electron Device Lett., vol. 32, no. 8, pp. 1095 –1097, Aug. 2011.

Chapter 6
[6.1] P.-C. Huang, L.-A. Chen, and J.-T. Sheu, “Electric-field enhancement of a gate-all-around nanowire thin-film transistor memory,” IEEE Electron Device Lett., vol. 31, no. 3, pp. 216 –218, March 2010.
[6.2] C.-Y. Wu, Y.-T. Liu, T.-C. Liao, M. Yu, and H.-C. Cheng, “Novel dielectric-engineered trapping-charge poly-Si-TFT memory with a TiN-Alumina-Nitride-vacuum-Silicon structure,” IEEE Electron Device Lett., vol. 32, no. 8, pp. 1095 –1097, Aug. 2011.
[6.3] Z.-H. Ye, K.-S. Chang-Liao, T.-C. Liu, T.-K. Wang, P.-J. Tzeng, C.-H. Lin, and M.-J. Tsai, “A novel SONOS-type flash device with stacked charge trapping layer,” Microelectron. Eng., vol. 86, no. 7-9, pp. 1863–1865, Jul. 2009.
[6.4] Y. Wang, D. Gao, W. Hwang, C. Shen, G. Zhang, G. Samudra, Y. Yeo and W. Yoo, “Fast erasing and highly reliable MONOS type memory wit HfO2 high-k trapping layer and Si3N4/SiO2 tunneling stack,” in IEDM Tech. Dig., 2006, pp. 1 –4.
[6.5] P.-H. Tsai, K.-S. Chang-Liao, T.-C. Liu, T.-K. Wang, P.-J. Tzeng, C.-H. Lin, L. Lee, and M.-J. Tsai, “Charge-trapping-type flash memory device with stacked high-k charge-trapping layer,” Electron Device Letters, IEEE, vol. 30, no. 7, pp. 775 –777, July 2009.