漏電流功耗在奈米尺度的電路設計中變成一個主要的挑戰，而且佔了總功耗的比率也越來越高。 最近有許多新穎的快取記憶體設計是根據程式的特性去降低漏電流功耗。其中一種為非對稱SRAM，它的特性是存位元”0”的時候可以降低漏電流功耗。 由於在嵌入式系統中，JPEG是其中一種主要的多媒體應用，所以降低JPEG影像的漏電流功耗會是有益的。 在本論文當中，我們提出了兩個演算法，value-position-switch演算法和code-bit-switch演算法，在非對稱SRAM上的時候，讓JPEG影像的內容能夠偏向位元”0”。Value-position-switch演算法和code-bit-switch演算法分別能夠讓JPEG影像當中的Huffman編碼的內容，最多能夠分別減少7.33%和25.20%的位元”1”。 這兩個演算法對於原本的JPEG編碼器在instruction count，cycle count和功耗方面所造成的額外負擔是可以忽略的(< 0.3%) 。 據我們所知，本論文是第一個在軟體的應用層級利用非對稱SRAM的特性來降低漏電流功耗。

[1] AGARWAL, A., MUKHOPADHYAY, S., RAYCHOWDHURY, A., ROY, K. AND KIM, C. H. 2006. Leakage Power Analysis and Reduction for Nanoscale Circuits. IEEE Micro, 26, 68-80.
[2] ASHISH, S., DENNIS, S. AND DAVID, B. 2004. Statistical optimization of leakage power considering process variations using dual-Vth and sizing. In Proceedings of the Proceedings of the 41st annual conference on Design automation (San Diego, CA, USA). ACM.
[3] AZIZI, N., NAJM, F. N. AND MOSHOVOS, A. 2003. Low-leakage asymmetric-cell SRAM. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 11, 701-715.
[4] BROOKS, D., TIWARI, V. AND MARTONOSI, M. 2000. Wattch: a framework for architectural-level power analysis and optimizations. SIGARCH Comput. Archit. News, 28, 83-94.
[5] BUTTS, J. A. AND GURINDAR, S. S. 2000. A static power model for architects. In Proceedings of the Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture (Monterey, California, United States). ACM.
[6] CHEN, G., LI, F., KANDEMIR, M., OZTURK, O. AND DEMIRKIRAN, I. 2006. Compiler-directed management of leakage power in software-managed memories. In Proceedings of the Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on.
[7] FLAUTNER, K., KIM, N. S., MARTIN., S., BLAAUW, D. AND MUDGE, T. 2002. Drowsy caches: simple techniques for reducing leakage power. In Proceedings of the Computer Architecture, 2002. Proceedings. 29th Annual International Symposium on .
[8] GAO, F. AND HAYES, J. P. 2006. Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 25, 2564-2571.
[9] JAMES, K., SIVA, N. AND ANANTHA, C. 2002. Subthreshold leakage modeling and reduction techniques. In Proceedings of the Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design (San Jose, California). ACM.
[10] JAYAKUMAR, N. AND KHATRI, S. P. 2007. An Algorithm to Minimize Leakage through Simultaneous Input Vector Control and Circuit Modification. In Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07.
[11] KETKAR, M. AND SAPATNEKAR, S. S. 2002. Standby power optimization via transistor sizing and dual threshold voltage assignment. In Proceedings of the Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on.
[12] KURSUN, V. AND FRIEDMAN, E. G. 2004. Sleep switch dual threshold Voltage domino logic with reduced standby leakage current. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 12, 485-496.
[13] LEI, C., DEMING, C. AND MARTIN, D. F. W. 2008. A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. ACM Trans. Des. Autom. Electron. Syst., 13, 1-15.
[14] LIN, Y. AND GANG, Q. 2007. Simultaneous input vector selection and dual threshold voltage assignment for static leakage minimization. In Proceedings of the Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design (San Jose, California).
[15] LIU, M., WEI-SHEN, W. AND ORSHANSKY, M. 2004. Leakage power reduction by dual-Vth designs under probabilistic analysis of Vth variation. In Proceedings of the Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on.
[16] PENNEBAKER, W. B. AND MITCHELL, J. L. 1993. JPEG Still Image Data Compression Standard Van Nostrand Reinhold.
[17] STEFANOS, K., ZHIGANG, H. AND MARGARET, M. 2001. Cache decay: exploiting generational behavior to reduce cache leakage power. In Proceedings of the Proceedings of the 28th annual international symposium on Computer architecture .
[18] TANAY, K., YIBIN, Y., JAMES, T., LIQIONG, W., STEVEN, B., VENKATESH, G., VIVEK, D. AND SHEKHAR, B. 2002. Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. In Proceedings of the Proceedings of the 39th conference on Design automation (New Orleans, Louisiana, USA). ACM.
[19] YOU, Y.-P., HUANG, C.-W. AND LEE, J. K. 2005. A sink-n-hoist framework for leakage power reduction. In Proceedings of the Proceedings of the 5th ACM international conference on Embedded software. (EMSOFT'05) (Jersey City, NJ, USA). ACM.
[20] YOU, Y.-P., LEE, C. AND LEE, J. K. 2006. Compilers for leakage power reduction. ACM Trans. Des. Autom. Electron. Syst., 11, 147-164.
[21] ZHANG, W., KANDEMIR, M., VIJAYKRISHNAN, N., IRWIN, M. J. AND DE, V. 2003. Compiler support for reducing leakage energy consumption. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition. (DATE'03).