鎖相迴路器之抖動效能研究｜國立清華大學博碩士論文庫

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研究生：	江宇晟 Yu-Chen Chiang
論文名稱：	鎖相迴路器之抖動效能研究 Jitter Performance Study For Phase-Lock Loop
指導教授：	黃柏鈞 Po-Chiun Huang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	中文
論文頁數：	78
中文關鍵詞：	鎖相迴路、抖動、壓控振盪器、電流補償
外文關鍵詞：	PLL, jitter, VCO, current compensation
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在很多電路的應用上，必須利用鎖相迴路器提供一個緊密跟隨輸入時脈的輸出時脈信號。例如時脈訊號的產生與資料回復以及頻率合成器、調頻器、解頻器的應用上。而隨著環璄所需時脈速度的增加，鎖相迴路器的抖動效能也越來越重要。而鎖相迴路器的抖動來源主要來自其非理想效應，如電源供應器雜訊、基板雜訊、壓控振盪器雜訊跟電流泵浦所產生的電流不對稱。
而在這篇論文主要提出了預估抖動效能的方法，來預估由不同雜訊源所造成的輸出抖動。而在一開始會先利用Hspice和Spectre去預估不同雜訊源所造成的相位雜訊，之後再利用相位雜訊轉抖動公式及雜訊轉換方程式來預估鎖相迴路器的輸出抖動。
而本次的研究主要把重點放在分析鎖相迴路器本身雜訊所產生的抖動。內容可分成理論分析及鎖相迴路器各個雜訊所造成的相位雜訊:
理論分析:
在這部份為分析各個不同的雜訊所造成的相位雜訊(phase noise)，然後利用相位雜訊(phase noise)轉抖動(jitter)公式來評估鎖相迴路器的抖動量。而所考慮的雜訊包括壓控振盪器的內部雜訊，輸入時脈的相位雜訊(phase noise)，迴路濾波器上電阻的熱雜訊，以及電流泵浦和相位頻率偵測器所產生的雜訊等。最後再利用雜訊轉換方程式求得最適合的系統參數設計。
鎖相迴路器各部份相位雜訊:
在這部份所考慮的相位雜訊主要包括壓控振盪器、相位頻率偵測器及電流泵浦所造成的電流不對稱、輸入相位雜訊等部份。

In many circuits, PLL must provide an output clock to follow the input clock closely.
Examples of applications that use PLL include clock and data recovery, clock synthesis, and synchronization, frequency synthesis and PLL modulator or de-modulator application. As environment clock speed rise up, the jitter performance for PLL is more and more important. The jitter source of PLL comes from many no ideal effect of PLL, such as power supply noise, substrate noise, VCO noise, and charge pump current mismatch.
This thesis proposes the prediction method of jitter performance, for estimate the output jitter comes from each noise source. Initially, Hspice and Spectre are used to estimate the output phase noise of each noise source in coordinate with phase-noise-to-jitter transfer function and noise transfer function (NTF) to estimate the PLL output jitter.
This thesis primary considered the noise created by phase-locked loop. Include thermal analysis and the phase noise created by each block in PLL.
Thermal Analysis:
This part primarily analysis the phase noise created by each block in PLL. Then use the phase noise to jitter equation to estimate the PLL output jitter.
PLL Each Block Phase Noise:
This park primarily consider VCO phase noise、current mismatch created by PFD/CP and input clock phase noise.

Contents
Introduction 1
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 ThesisOrganization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Phase-Locked Loop Design Background 3
1 Phase-LockedLoopDesignConcept . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 PLL Background Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 PLLBuildingBlocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Phase-FrequencyDetector . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Charge Pump and Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 Voltage Control Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Second-Order Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5 SystemParameterDesign . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Jitter Estimate for Each Block in PLL 13
1 Jitter Estimate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.1 Phase Noise to Jitter Transfer Function: . . . . . . . . . . . . . . . . . . . 13
1.2 NoiseTransferFunction . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2 Voltage Control Oscillator Output Phase Noise . . . . . . . . . . . . . . . . . . . 16
2.1 ImpulseSensitivityFunction . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 Voltage Controlled Oscillator Output Phase Noise Optimization . . . . . . 18
3 ChargePumpOutputPhaseNoise . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 Clock feed-through and current mismatch . . . . . . . . . . . . . . . . . . 21
3.2 Device thermalnoise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4 Input Phase Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1 SignalGeneratorPhaseNoise . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2 Crystal Oscillator Phase Noise . . . . . . . . . . . . . . . . . . . . . . . . 26
5 Loop Filter Resistor Thermal Noise . . . . . . . . . . . . . . . . . . . . . . . . . 28
Prototype Verification 30
1 Phase-LockedLoopDesignConcept . . . . . . . . . . . . . . . . . . . . . . . . . 30
2 Voltage Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.1 Self-Biased Voltage Controlled Oscillator . . . . . . . . . . . . . . . . . . 31
2.2 Voltage Controlled Oscillator Output Phase Noise . . . . . . . . . . . . . . 34
3 Phase-FrequencyDetector andChargePump . . . . . . . . . . . . . . . . . . . . 35
3.1 Phase-FrequencyDetector . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.2 ChargePump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.3 ChargePumpOutputPhaseNoise . . . . . . . . . . . . . . . . . . . . . . 38
4 Phase-LockedLoopSystemParameterDesign . . . . . . . . . . . . . . . . . . . . 39
4.1 SystemParameterDesign . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5 MeasurementResult . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Low-Jitter PLL Design 45
1 Phase-LockedLoopDesignConcept . . . . . . . . . . . . . . . . . . . . . . . . . 45
2 Voltage Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.1 Compare Each Structure with Power Supply and Ground Noise . . . . . . 46
2.2 Voltage Control Oscillator Output Phase Noise . . . . . . . . . . . . . . . 50
3 Phase-FrequencyDetector andCurrentMatchingChargePump . . . . . . . . . . . 51
3.1 Phase-FrequencyDetector . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.2 CurrentMatchingChargePump . . . . . . . . . . . . . . . . . . . . . . . 52
3.3 ChargePumpOutputPhaseNoise . . . . . . . . . . . . . . . . . . . . . . 53
4 Phase-LockedLoopSystemParameterDesign . . . . . . . . . . . . . . . . . . . . 55
5 PredictionSpecifiction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Conclusion and Future Work 60
1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2 FutureWork . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

                                

A. Hajimiri, T. H. Lee, “Jitter and Phase Noise in Ring Oscillator”, IEEE J. Solid-State Circuits, vol. 34, pp. 790–804, June. 1999.

A. Hajimiri, T. H. Lee, “A General Theory of Phase Noise in Electrical Oscillators”, IEEE J. Solid-State Circuits, vol. 33, pp. 179-194, February 1998.

C.H. Park, B. Kim, “A Low-Noise, 900-MHz VCO in 0.6-um CMOS”, IEEE J. Solid-State Circuits, vol. 34 pp. 586-591, May 1999.

J. G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques”, IEEE J. Solid-State Circuits, vol. 31, pp.1723-1732, November 1996.

M. Mansuri, C.K. Ken Yang, ”Jitter Optimization Based on Phase-Locked Loop Design Parameters”, IEEE J. Solid-State Circuits, vol. 37, pp.1375-1382, November 2002.

W. F. Egan, “Modeling Phase Noise in Frequency Dividers”, IEEE Trans. Ultrason, Ferroelectr, Freq, Contr, vol. 37, pp.307-315, July 1990.

L. Luh, J. Choma, Jr, and J. Draper, “A High-Speed Fully Differential Current Switch”, IEEE, Trans. Circuits and Systems, vol. 47, pp.358-363, April 2000.

V. F. Kroupa, “Jitter and Phase Noise in Frequency Dividers”, IEEE, Trans. Instrumentation and Measurement, vol. 50, pp.1241-1243, October 2001.

M. Soyuer, J. F. Ewen, and Harry L. Chuang, “A Fully Monolithic 1.25GHz CMOS Frequency Synthesizer”, IEEE, 1994.

C.K. Ken Yang, “A Low-Power Adaptive Bandwidth PLL and Clock Buffer With Supply-Noise Compensation”, IEEE J. Solid-State Circuits, vol.38, pp. 1804-1812, November 2003.

M. Mansuri, A. Hadiashar, C.K. Ken Yang, ”Methodology for On-Chip Adaptive Jitter Minimization in Phase-Locked Loops”, IEEE, Trans. Circuits and Systems, vol.50, pp. 870-878, November 2003.

C.C. Su, “Design of Low-Spurious-Tones CMOS Frequency Synthesizer for 2.4FHz Transceiver.” NCTU Master Thesis, 2002.

P. Heydari, “Design of Ultrahigh-Speed Low-Voltage CMOS CML Buffers and Latches”, IEEE Trans. VLSI, vol. 12, pp.1081-1093, Oct, 2004.

B. Kim, “A Low-Noise Phase-Locked Loop Design by Loop Bandwidth Optimization”, IEEE, J Solid-State Circuits, vol. 35, pp.807-815, June, 2000.

C.K. King Yang, “A Low-Power Adaptive Bandwidth PLL and Clock Buffer with Supply-Noise Compensation”, IEEE J.Solid-State Circuits, vol. 38, pp.1804-1812, Nov, 2003.

H.G. Ryu, H.S. Lee, ”Analysis and Minimization of Phase Noise of the Digital Hybrid PLL Frequency Synthesizer”, IEEE Trans. on Consumer Electronics, vol. 48, pp.304-312, May, 2002

A. Lehner, R. Weigei, A. Hajimiri, “Design of a Novel Low-Power 4th-Order 1.7GHz CMOS Frequency Synthesizer for DCS-1800”, IEEE ISCAS, pp.637-640, May, 2000

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