為了增加競爭優勢，晶圓製造廠需要藉由增加每片晶圓上晶粒的數量來提昇生產力以達到降低平均生產成本的目的。目前已發展出許多最佳化的晶圓曝光演算法來提升每片晶圓上晶粒的數量，然而每片晶圓上晶粒的數量會受到晶粒的大小所影響，包括晶粒的長度、寬度以及面積。但是在晶粒設計的階段並沒有考慮到所設計的晶粒形狀大小對於之後在製造階段所造成的曝光影響。本研究整合晶圓製造及設計兩端以可製造性設計提供較佳的晶粒大小設計建議來改善整體的晶圓製造效率，針對特殊的空間性資料，提出一個兩階段的決策樹演算法，找出每片晶圓上晶粒的數量和晶粒大小形狀之間的關係，並萃取出其中的規則來建立設計建議系統以供晶粒設計者參考，此兩階段決策樹演算法可提高預測準確度並降低樹的複雜性，讓使用規則之搜尋過程更加有效率。
以此決策樹演算法為基礎，建立一個晶粒設計最佳化的分析架構，並以一半導體晶圓製造廠轉換後的實際資料作為驗證，可建議出最佳晶粒設計來最大化晶粒數量並同時降低生產成本以提高晶圓製造廠的產出。

In order to enhance the competitive advantages of wafer fabs, it is crucial for wafer fabs to increase the number of gross dies per wafer to reduce average die cost through productivity improvement. However, gross die number is influenced by die size in design phase, while the existing size of integrated circuit die was designed without considering the effect on wafer throughput in fabrication phase. This research aims to bridge the gap between design and wafer exposure by providing design advice with optimal feature size of integrated circuit device in the design phase so as to improve the overall wafer effectiveness in fabrication. In particular, a two-phase decision tree algorithm for die size optimization is developed to construct the rules between the numbers of gross dies per wafer and mask utilization to the die feature including length, width, and area. Without losing generality, an empirical study has been done for validation by using transformed data from a fab in Taiwan. The results show practical viability, in which the IC designer can easily use these extracted rules to design optimal integrated circuit die size for maximizing the gross die number per wafer and reducing the fabrication cost at the same time.

鄭仁傑 (2003)，以混和決策樹方法分析有相互關係之半導體資料，國立清華大學工業工程與工程管理研究所碩士論文。
賴彥中 (2005)，發展主幹式決策樹法則以提昇半導體良率之研究-以DRAM廠為實證，國立清華大學工業工程與工程管理研究所碩士論文。
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