低溫複晶矽薄膜電晶體(LTPS TFT)是目前實現高效能薄膜電晶體主動式液晶顯示器(AMLCD)最可靠的技術，低溫複晶矽薄膜電晶體擁有比非晶矽薄膜電晶體更高的場效載子移動率(field effect mobility)，因此可以有效縮小畫素設計面積。為了達到高解析度以及高製程再現性，電漿乾蝕刻製程廣泛的使用在低溫複晶矽薄膜電晶體的製作流程裡。在這篇論文，我們廣泛的探討電漿蝕刻製程所帶來的電漿製程損傷(PPID)效應並且評估各種不同的製程以修補及抵抗低溫複晶矽薄膜電晶體生產過程中所會遇到的電漿製程損傷效應。
首先我們探討低溫複晶矽薄膜電晶體生產過程中複晶矽薄膜蝕刻所造成的電性飄移與劣化，我們設計的不同的元件長度與寬度以協助我們釐清此電漿損傷效應的機制，我們同時也利用熱載子應力壓迫(hot-carrier stress)了解元件的可靠度。同時我們也研究不同製程對於複晶矽薄膜電漿損傷的修補效能，我們利用不同的熱退火製程以及電漿後處理製程進行修補，企圖對於被損傷的複晶矽薄膜找出較佳之修補製程。由研究結果得知，含有氫原子的電漿後處理製程以及雷射再結晶製程都可以有效修補電漿製程所導致的損傷效應。修補製程得以改善的主要機制是氫原子利用電漿鈍化可以有效的修補元件之深層缺陷，而雷射再結晶製程則是將受損元件邊緣之複晶矽薄膜重新結晶所造成之結果。
第二部份我們針對低溫複晶矽薄膜電晶體生產過程中金屬閘極蝕刻所造成的電性飄移與元件劣化進行研究，我們也利用不同的元件長度與寬度協助釐清此電漿損傷效應的機制。在低溫複晶矽薄膜電晶體設計中，雙閘極(dual-gate)電晶體因為可以分散與降低閘極與汲/源極之電場梯度，因此可以有效降低漏電流。可是很不幸地，此設計卻會因為雙倍的閘極邊緣暴露在電漿製程中而比單閘極的元件受到更嚴重的電漿損傷。在本章我們也同時利用閘極高電壓壓迫(high field gate bias stress)了解元件的可靠度與元件損傷程度。我們也利用不同的熱退火製程以及電漿後處理製程進行修補，企圖對於因為閘極電漿蝕刻製程被損傷的元件找出較佳之修補製程。由研究結果得知，氨氣的電漿後處理製程有最好的修補損傷效應，此乃由於氨電漿中的氫原子將可有效的填補複晶矽之懸浮鍵，及氮原子會堆積在二氧化矽/複晶矽表面形成介面保護。 同時，利用多一層薄的氮化矽薄膜在原本的二氧化矽閘極絕緣層之上，除了可以有效抵擋電漿接觸傷害之外也可以有效修補複晶矽薄膜的缺陷。
另外我們也探討金屬閘極蝕刻過程中因為天線效應(antenna effects)所導致的元件損傷，由實驗結果得知，在較高天線比例以及較厚的閘極電漿蝕刻製程下會導致嚴重的電漿損傷效應。由天線效應所導致的元件損傷主要機制是電漿不均勻所造成的閘極介電層之損傷，因此此嚴重損傷將無法由一般的熱退火製程甚至電漿後處理製程進行修補與改善。

Low temperature polycrystalline silicon (LTPS) technology is the most promising technology to manufacture high performing thin film transistors (TFTs). LTPS TFT with high mobility can reduce device size more than the conventional amorphous silicon TFT. To achieve high resolution and good process repetitiousness, plasma dry etch processes were wisely adopted in LTPS TFT manufacturing. In this thesis, we extensively studied the plasma process induced damage (PPID) effects and evaluated various processes in order to recover and against plasma process induced damage in LTPS TFT fabrication.
At first, the device characteristics and degradation of LTPS TFT in poly-Si plasma process were investigated. Different channel widths and lengths were designed to discuss the PPID effects of poly-Si etch process. Device reliability was also studied by electrical stressed, such as hot carrier stressing, to reveal the damage effects. In the meanwhile PPID recovery of LTPS TFT in poly-Si plasma process was also investigated. Thermal anneal processes with different ambient and post-etched plasma treatments were carried out to recover the damage effects by PPID. Furthermore, post-etch treatments with plasma in hydrogen ambient and laser anneal have been demonstrated to significantly remove PPID effects. It is believed that the deep trapping states can be repaired by hydrogen species, and the damaged channel edge of the active region are re-crystallized by laser anneal, respectively.
In the second part, the metal gate plasma process on the electrical characteristics and degradation of LTPS TFT were investigated. Different channel widths and lengths were designed to discuss the PPID effects of metal gate etch process. Devices with thick metal gates have worse electrical reliability after PBTI tested due to plasma process induced latent damage. Dual gate TFT is adopted to suppress leakage current by reducing the electric field from gate to source/drain. The reliability of dual gates TFT is degraded due to serious PPID effects, particularly for device with thick metal gate. Dual gates devices incur serious plasma damage due to twice as many exposed channel edges as single gate devices in the metal gate etch process. Reliability and trap density were also studied by electrical stressing, such as high filed gate voltage stressing, to reveal the damage effects. In the meantime, PPID recovery of LTPS TFT in metal gate plasma process was studied. Thermal anneal process with different ambient and post-etched plasma treatment were carried out to recover the damage effects. It is demonstrated that the post-etch treatments with thermal annealing and plasma in NH3 ambient can recover PPID because hydrogen species can repair the trapping states. Gate dielectric with thin silicon nitride stacked upon silicon oxide was adopted to resist PPID. Furthermore, the electrical characteristics of LTPS TFT show significantly improvement by post-etch NH3 treatment on thin silicon nitride stacked with silicon oxide.
In addition, we have also studied antenna effects of LTPS TFT during metal gate plasma etch process. Devices with a high antenna ratio, and especially those that undergo thick metal patterning, exhibit obvious degradation and poor reliability when stressed. These results are concluded to be caused by damage to the gate oxide. Such devices will exhibit huge damage and consequent degradation upon electrical stressing. Unfortunately, such damaged devices cannot be easily recovered by thermal or hydrogenation treatment.

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