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研究生： 黃鼎凱
Huang, Ding-Kai
論文名稱： 在平台式三維積體電路設計中考慮TSV數量限制的匯流排架構合成器
A TSV-Number-Constrained Bus System Synthesizer for Platform-based 3D IC Design
指導教授： 林永隆
Lin, Youn-Long
口試委員:
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年： 2009
畢業學年度： 98
語文別： 英文
論文頁數： 39
中文關鍵詞： 三維積體電路 、匯流排
相關次數： 點閱：1  下載：0 
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    • 本論文針對一個名為Chipsburger的平台式三維積體電路設計方法提出一個匯流排架構合成器。Chipsburger透過製造的重複利用來降低成本，但也對晶片層之間的溝通架構造成限制，此外晶片良率會隨著TSV的增加而降低。

    我們的目標是在TSV數量的限制下設計一個適合各個應用的匯流排架構。我們使用模擬退火演算法針對Chipsburger產生出實作成本最低的匯流排架構。

    實驗結果顯示，此匯流排合成器能針對不同的TSV數量限制產生出適合的匯流排架構。

    Abstract III Contents IV List of Figures V List of Tables VI Chapter 1 Introduction 1 1.1 Three-Dimensional Integrated Circuits 1 1.2 A Platform-based 3D IC Design Methodology 2 Chapter 2 Related Work 6 Chapter 3 Proposed Bus Topology Synthesizer 9 3.1 Assumptions 9 3.1.1 Bandwidth Requirement Modeling 9 3.1.2 Bus topology 11 3.2 Problem Formulation 15 3.3 An Illustrative Example 16 3.2.1 Flexibility of Multiple-Access Port 19 3.2.2 Effects of TSV Number Constraint 19 3.4 Proposed Bus Topology Synthesizer 20 Chapter 4 Experimental Results 24 4.1 Test Cases 24 4.2 Bus Topology Synthesis 28 4.2.1 Simulated Annealing Optimization 28 4.2.2 Result of Bus Topology Synthesis 31 Chapter 5 Conclusion 37 Bibliography 38

    [1] J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, M. J. Interrante, C. S. Patel, R. J. Polastre, K. Sakuma, R. Sirdeshmukh, E. J. Sprogis, S. M. Sri-Jayantha, A. M. Stephens, A. W. Topol, C. K. Tsang, B. C. Webb, and S. L. Wright,”Three-Dimensional Silicon Integration,” IBM Journal of Research and Development, vol. 52, no. 6, pp.553-569, November 2008
    [2] ARM AMBA Specification and Multi Layer AHB Specification, Available:
    http://www.arm.com/products/solutions/AMBAHomePage.html
    [3] IBM On-Chip CoreConnect Bus Architecture Specification, Available: https://www-01.ibm.com/chips/techlib/techlib.nsf/products/CoreConnect_Bus_Architecture
    [4] S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, “Optimization by Simulated Annealing,” Science, vol. 220, no. 4598, pp. 671–680, May 1983
    [5] Srinivasan Murali, Luca Benini, and Giovanni De Micheli, “An Application-Specific Design Methodology for On-Chip Crossbar Generation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, pp. 1283-1296, July 2007
    [6] Kanishka Lahiri, Anand Raghunathan, and Sujit Dey, “Design Space Exploration for Optimizing On-Chip Communication Architectures,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, pp. 952-961, June 2004
    [7] Sudeep Pasricha, Nikil Dutt, and Mohamed Ben-Romdhane, “Constraint-Driven Bus Matrix Synthesis for MPSoC,” Proceedings of Asia and South Pacific Design Automation Conference, pp. 30-35, January 2006
    [8] Nattawut Thepayasuwan and Alex Doboli, “Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip,” Proceedings of Design, Automation and Test in Europe, vol. 1, pp. 108-113, February 2004
    [9] Sudeep Pasricha and Nikil Dutt, “COSMECA: Application Specific Co-Synthesis of Memory and Communication Architecture for MPSoC,” Proceedings of Design, Automation and Test in Europe, vol. 6, pp. 1-6, March 2006
    [10] Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita, and Luca Benini, “A Low-Overhead Fault Tolerance Scheme for TSV-Based 3D Network on Chip Links,” Proceedings of International Conference on Computer-Aided Design, pp. 598-602, November 2008

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