一個應用於感應器陣列之使用校正10位元行平行之逐次逼近寄存型類比數位轉換器

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研究生：	蘇聖航 Su, Sheng-Hang
論文名稱：	一個應用於感應器陣列之使用校正10位元行平行之逐次逼近寄存型類比數位轉換器 A 10-bit Column Parallel SAR ADC with Calibration for Sensor Array Applications
指導教授：	謝志成 Hsieh, Chih-Cheng
口試委員:	鄭桂忠陳新邱進峯
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2013
畢業學年度：	101
語文別：	英文
論文頁數：	68
中文關鍵詞：	類比數位轉換器、行平行、多分段電容式
外文關鍵詞：	analogue-to-digital converter, column-parallel, multiple segmented charge redistribution capacitive
相關次數：	點閱：4 下載：0
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摘要
本論文提出一個應用於感應器陣列式之十位元行平行處理(Column-Parallel)的類比數位轉換器(Analog-to-Digital Converter, ADC)，為降低單一類比數位轉換器之功耗，本論文採用漸近式類比數位轉換器(Successive Approximation ADC)的架構，並利用功耗較低的電容式數位類比轉換器(Capacitive Digital-to-Analog Converter)來產生類比數位轉換過程中所需的參考電位。由於傳統電容式數位類比轉換器是造成漸進式類比數位轉換器面積過大的主要原因，在行平行處理的應用中由於要將之實現在行寬(Column Pitch)中，因此，本論文提出一多分段電容式數位類比轉換器(Multi-Segmented Capacitive DAC)以降低數位類比轉換器所占的面積與功耗。為了解決分段DAC固有的不匹配問題，本論文提出了一種新的數位校正方法，使得SNDR從51.79dB提升至57.63dB。
為了驗證本電路，本論文利用0.18微米CMOS製程來實現一原型實驗晶片。本實驗晶片操作在1V 的供給電源和4MS/ s 的採樣速率。在接近Nyquist 頻率所測得的有效位元數（ENOB），是9.28 位元。在經過校正後差動非線性誤差(differential non-linearity, DNL)由 +0.52 / -1 LSB 提升至 +0.62 / -0.65 LSB，積分非線性誤差(integrated non-linearity, INL)由 +3.2 / -3.1 LSB 提升至 +0.64 / -0.48 LSB。整顆晶片總功耗為53.5 微瓦，所計算的等效figure of merit（FoM）則為21.5fJ/Conversion-step。

ABSTRACT
This thesis proposes a 10-bit column-parallel successive approximation (SAR) analogue-to-digital converter (ADC) used for sensor array applications. A multiple segmented charge redistribution capacitive digital-to-analog converter (MS-C-DAC) is employed to reduce the area and power consumption. To solve the inherent mismatch issue of segmented DAC, a new digital calibration method is proposed, which improves SNDR from 51.79 dB to 57.63 dB.
The prototype experimental chip is fabricated by 0.18um CMOS technology. The prototype ADC operates with 1V supply and 4MS/s sampling rate. The measured effective number of bits (ENOB) at near Nyquist frequency is 9.28-bit. The differential non-linearity is reduced from +0.52 / -1 LSB to +0.62 / -0.65 LSB, and the integrated non-linearity is improved from +3.2 / -3.1 LSB to +0.64 / -0.48. The total power consumption of 53.5uW is achieved, and the resultant figure of merit (FoM) is 21.5fJ/Conversion-step.

CONTENTS
ABSTRACT    II
CONTENTS    III
CHAPTER 1 INTRODUCTION    6
1    MOTIVATION    6
2    THESIS ORGANIZATION    9
CHAPTER 2 ADC OVERVIEW    10
1    SINGLE SLOPE ADC    10
2    Cyclic ADC    12
3    Delta-Sigma ADC    13
4    SUCCESSIVE APPROXIMATION REGISTER (SAR) ADC    14
5    THE EXISTING WORKS COMPARISONS    16
6    SUMMARY    17
CHAPTER 3 SUCCESSIVE APPROXIMATION ADC    18
1    PERFORMANCE METRICS OF SAR ADCS    18
1.1    Resolution    18
1.2    Quantization error    19
1.3    Differential Nonlinearity (DNL) and Integral Nonlinearity (INL)    19
1.4    Signal-to-Noise Ratio (SNR)    20
1.5    Effective Resolution    20
1.6    Figure of Merit (FoM)    21
2    GLOBAL SAR ADC    21
2.1    Single-ended SAR ADC    21
2.2    Differential SAR ADC    22
3    SAMPLE AND HOLD    23
3.1    Charge Injection and Clock Feedthrough    24
3.2    Thermal Noise    25
3.3    Modified Sample-and-Hold Circuit    26
3.3.1    Complementary Sampling Switch    26
3.3.2    Bootstrap Sampling Switch    27
3.4    Design Consideration    28
4    COMPARATOR    28
5    DIGITAL-TO-ANALOG CONVERTER    29
5.1    Binary Weighted DAC    29
5.2    Split DAC    30
5.3    Design Consideration    31
6    SUCCESSIVE APPROXIMATION REGISTER    32
7    SUMMARY    32
CHAPTER 4 PROPOSED SAR ADC DESIGN    33
1    CAPACITIVE DAC DESIGN    33
1.1    Case 1: Cs1<16/15C    35
1.2    Case 2: Cs1>16/15C    36
1.3    Set Cs1 Size    37
2    SAMPLE-AND-HOLD DESIGN    38
3    COMPARATOR DESIGN    42
4    ASYNCHRONOUS SAR LOGIC AND DAC CONTROL LOGIC CHOICE    44
5    CALIBRATION METHODOLOGY    44
5.1    Error Quantization    45
5.2    Calibration Phase    46
6    SIMULATION RESULT    47
7    SUMMARY    52
CHAPTER 5 CHIP IMPLEMENTATION AND MEASUREMENT    53
1    CHIP IMPLEMENTATION    53
2    MEASUREMENT ENVIRONMENT SETUP    54
3    MEASUREMENT RESULTS    55
3.1     Static Performance    55
3.2     Dynamic Performance    56
3.3     Measurement for multi-columns    59
4    PERFORMANCE SUMMARY AND COMPARISON    60
5    SUMMARY    62
CHAPTER 6 CONCLUSIONS    63
1    SUMMARY    63
2    FUTURE WORK    64
BIBLIOGRAPHY    65

                                

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