在鎖相迴路(Phase-Locked Loop, PLL)的設計中，頻寬的大小影響了迴路的鎖定時間(Locking time)與鎖定狀態下迴路的相位抖動(Jitter)。藉由提高迴路頻寬的方式，可以加快鎖定時間，可是提高頻寬的同時，反而會使得相位抖動變大。為了同時得到較佳的鎖定時間與較小的相位抖動，因此動態調整迴路頻寬的適應性鎖相迴路(Adaptive PLL)的概念被提出，讓鎖相迴路根據不同的鎖定情形，來調整迴路的頻寬。
此篇論文研究中，採用雙緣相位頻率偵測器(Dual-edge Phase-Frequency Detector)來比較輸入訊號和鎖相迴路中回授訊號正緣的相位差異與負緣的相位差異，控制電荷幫浦對低通濾波器充放電，相較於傳統相位頻率偵測器多了一倍的比對結果，增加了電流幫浦充放電的次數，因此可以加快迴路的鎖定速度。不過因為雙緣相位頻率偵測器會增加迴路的雜訊，因此在接近鎖上時，切換為單緣相位頻率偵測器，來減少輸出頻率的鏈波。另外雙緣相位頻率偵測器的訊號經過簡單的處理後，即可得知迴路的鎖定狀態，並藉此來調整頻寬。
本研究主要是結合雙緣相位頻率偵測器和動態調整頻寬的概念，將雙緣相位頻率偵測器的訊號經過簡易頻寬控制單元(Bandwidth Control Unit, BCU)的處理，來判斷何時切換頻寬，來達到快速鎖定及縮小相位抖動的目的。其鎖定狀態的判斷，比一般鎖相迴路的使用延遲單元 (Delay cell) 所組成的相位誤差偵測器又擁有更佳擴充性和應用性以及抗製程變異能力。

In the phase-locked loop (PLL) design, the locking time and the jitter depend on the loop bandwidth. Increasing the loop bandwidth of the PLL can reduce the locking time, but also increase the jitter. In order to gain the fast locking time and the low jitter, the adaptive PLL concept which uses dynamic bandwidth adjustment is presented. Therefore, the loop bandwidth switch mechanism is required to monitor the PLL locking status and adjust the loop bandwidth.
In this thesis, the dual-edge phase-frequency (DE-PFD) detector is well integrated in our adaptive PLL. The DE-PFD speeds up the locking time by detecting the phase difference between reference clock signal and PLL’s feedback signal of the divider circuit in both rising edge and falling edge simultaneously. Meanwhile, the proposed signal generated from the DE-PFD can control the charge pump to charge/discharge low pass filter to switch the loop bandwidth. Compared with the conventional adaptive PLL, the locking detector using DE-PFD save the hardware overhead and switch the bandwidth smoothly. However, the DE-PFD not only speeds up the locking time but also increases the noise of the PLL. Therefore, the DE-PFD is switched to the single-edge PFD to decrease the noise when the PLL is locked.
The proposed adaptive PLL combines the dynamic bandwidth concept with the DE-PFD to speed up the locking time. It can make a decision of the switch timing easily by processing the signals of the DE-PFD with the bandwidth control unit (BCU). The locking status detection algorithm of the proposed circuit is simple to be implemented and also can avoid the uncertainty issue from process variation. With the adaptive bandwidth and the dual-edge PFD, the time improvement is 59.2% by simulation.

[1] J. Lee, and B. Kim, “A low-noise fast-lock phase-locked loop with adaptive bandwidth control,” IEEE J. Solid-State Circuits, vol. 35, no. 8, pp. 1137-1145, 2000.
[2] C.-Y. Yang, and S.-I. Liu, “Fast-switching frequency synthesizer with a discriminator-aided phase detector,” IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 1445-1452, 2000.
[3] Y. Woo, Y. M. Jang, and M. Y. Sung, “Phase-locked loop with dual phase frequency detectors for high-frequency operation and fast acquisition,” Microelectronics Journal, vol. 33, no. 3, pp. 245-252, 2002.
[4] K.-H. Cheng, W.-B. Yang, and C.-M. Ying, “A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loop,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 50, no. 11, pp. 892-896, 2003.
[5] Y. S. Choi, H. H. Choi, and T. H. Kwon, “An adaptive bandwidth phase locked loop with locking status indicator,” in Proc. of KORUS, Science and Technology, 2005, pp. 826-829.
[6] Y. Ge, W. Feng, Z. Chen et al., “A fast locking charge-pump PLL with adaptive bandwidth,” in 6th International Conference On ASIC, 2005, pp. 383-386.
[7] J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723-1732, 1996.
[8] C.-L. Ti, Y.-H. Liu, and T.-H. Lin, “A 2.4-GHz fractional-N PLL with a PFD/CP linearization and an improved CP circuit,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), 2008, pp. 1728-1731.
[9] E. J. Hernandez, and A. Diaz Sanchez, “Positive feedback CMOS charge-pump circuits for PLL applications,” in Proc. IEEE Midwest Symposium on Circuits and Systems (MWSCAS), 2001, pp. 836-839.
[10] B. Razavi, Design of Integrated Circuits for Optical Communications: McGraw-Hill, Inc. NY, USA, 2003.
[11] Y.-F. Kuo, R.-M. Weng, and C.-Y. Liu, “A Fast Locking PLL With Phase Error Detector,” in Proc. IEEE Conference on Electron Devices and Solid-State Circuits, 2005, pp. 423-426.
[12] S. I. Ahmed, and R. D. Mason, “A dual edge-triggered phase-frequency detector architecture [frequency synthesizer applications],” in Proc. International Symposium on Circuits and Systems (ISCAS), 2003, pp. I-721-I-724.
[13] Y.-P. Zhou, Z.-Q. Lu, and Y.-Z. Ye, “A Double-Edge-Triggered Phase Frequency Detector for Low Jitter PLL,” in Proc. International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2006, pp. 1963-1965.
[14] A. A. Abidi, “Phase Noise and Jitter in CMOS Ring Oscillators,” IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1803-1816, 2006.
[15] L.-K. Soh, M. S. Sulaiman, and Z. Yusoff, “Fast-Lock Dual Charge Pump Analog DLL using Improved Phase Frequency Detector,” in Proc. International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2007, pp. 1-5.
[16] J. Lan, F. Lai, Z. Gao, H. Ma, and J. Zhang, “A nonlinear phase frequency detector for fast-lock phase-locked loops,” in Proc. IEEE International Conference on ASIC (ASICON), 2009, pp. 1117-1120.
[17] T. H. Lin, C. L. Ti, and Y. H. Liu, “Dynamic Current-Matching Charge Pump and Gated-Offset Linearization Technique for Delta-Sigma Fractional-N PLLs,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 5, pp. 877-885, 2009.