在本論文中，我們在利用集結式電槳輔助化學氣相沈積系統，在複晶矽薄膜上形成氧化層-氮化層-氧化層的架構做為非揮發記憶體，此記憶體可用於系統面板以增進面板的附加價值。在操作記憶體元件過程中，我們會施加偏壓達成臨界電壓偏移1伏特，以做為我們對記憶特性的需求，然而在複晶矽薄膜上施加偏壓容易造成複晶矽薄膜劣化，這與我們在單晶矽非揮發性記憶體不同，因複晶矽薄膜有許多結晶介面，介面一經偏壓作用，容易劣化而影響元件特性，因此在本論文中，我們使用了在N與P兩種不同的通道，利用不同的寫入模式（富勒－諾得漢穿隧穿遂與熱電子注入），和不同的抹除模式(富勒－諾得漢穿隧穿遂，能帶對能帶穿遂輔助電洞注入，通道電洞注入 )，觀察記憶元件之記憶特性，藉由電壓-電流圖的變化，配合能帶圖的分析，我們可以在不同操作模式時，了解載子受到水平電場與垂直電場的影響而有不同的注入模式，找出最適合寫入/抹除模式在低溫複晶矽揮發性記憶體使用，並探討操作模式對複晶矽薄膜的影響，而透過我們的實驗成果，我們可以在P-通道的低溫複晶矽非揮發記憶體，寫入/抹除0.01杪的脈衝時間下，有1.6伏特的記憶視窗，而操作寫入/抹除5×104循環後，依然可以維持1伏特以上的記憶特性。

Development of the “System-on-glass” display with low temperature Poly-Si (LTPS) TFT has rapidly advanced recently. The display incorporated with nonvolatile memories becomes an attractive topic. In this study, nonvolatile memories using low temperature poly-Si process with oxide-nitride-oxide (ONO) stack structure on glass was studied and fabricated. The memory window should be lager than 1V to meet the logic memory circuit. The operation of nonvolatile memory is giving differential bias combination on gate, source and drain, in order to program and erase. The traps of grain boundary in poly-Si, however, maybe degrade the performance in some operational mode. There could be some reliability issue in low temperature poly-Si nonvolatile memory. We therefore investigate various operational modes in N-channel and P-channel so as to search which operational mode is reliable. Using Fowler-Nordheim tunneling to program and hot hole injection to erase, the threshold voltage memory has 1.5V at P/E time of 100ms. After 104 P/E cycles, the devices maintain a 1.5v threshold voltage memory.

Chapter 1
[1.1] H.Oshima and S.Morozumi,”Future trends for TFT integrated circuits on glass substrates”, IEDM Tech. Dig.,157(1989)
[1.2] M.Stewart, R.S.Howell, L.Pires, and M.K.Hatalis, “Polysilicon TFT technology for active matrix OLED displays“, IEEE Trans. Electron Devices, vol 48,pp. 845-821, 2001
[1.3] Y. Nakajima, Y. Kida, M. Murase, Y.Toyoshima, Y. Maki, “latest development of “system-on-glass” display with low temperature Poly-Si TFT”, SID 04 DIGEST, pp.864, (2004)
[1.4] H. Kimura, T. Maeda, T. Tsunashima,T. Morita, H. Murata, S. Hirota, H. Stao, “A 2.15 inch QCIF reflective color TFT-LCD with digital memory on glass (DMOG)”, SID 01 Digest, PP.268 , (2001)
[1.5] M. Senda Y. Tsutsui, R. Yokoyama, K. Yoneda, “Ultra-low-power polysilicon AMLCD with full integration”, SID 02 Digest, PP.790 , (2002)
[1.6] H. Tokioka, M. Agari, M. Inoue, T. Yamamoto, “low power consumption TFT-LCD with dynamic memory embeded in pixels” ,SID 01 Digest, PP.280 , (2001)
[1.7] N. I. Lee, J. W. Lee, S. H. Hur, H. S. Kim, and C. H. Han, “Effect of bottom polysilicon doping on the reliability of interpoly oxide grown using electron cyclotron resonance N2O-plasma,” Jpn. J. Appl. Phys., vol. 37, no. 3B, pt. 1, p. 1125, 1998.
[1.8] N. D. Young, G. Harkin, R. M. Bunn, D. J. McCulloch, and I. D. French, IEEE Trans. on Electron Devices, 43(11), 1930(1996).
[1.9] D. Kahng and S. M. Sze, “A floating gate and its application to memory devices”, Bell Syst. Tech, J., 46, 1288 (1967)
[1.10] M. H. White, Y. Yang, A. Purwar, and M. L. French, ”A low voltage SONOS nonvolatile semiconductor memory technology”, IEEE Int’l Nonvolatile Memory Technology Conference, 52 (1996).
[1.11] M. H. White, D. A. Adams, and J. Bu, “On the go with SONOS”, IEEE circuits & devices, 16, 22 (2000).
[1.12] H. E. Maes, J. Witters, and G. Groeseneken, Proc. 17 European Solid State Devices Res. Conf. Bologna 1987, 157 (1988)
Chapter 2
[2.1] William D.Brown, Joe E.brewer “Nonvolatile Semiconductor Memory Technology : A Comprehensive guide to understanding and using NVSMdevices,”,IEEE press.
[2.2] M.Lenzlinger,..” Fowler-Nordheim Tunneling in thermall grown SiO2” ,J, App. Phys.,vol. 40, p.278, 1969
[2.3] P. E. Cottrell, R. R. Trountman, “Hot electron emission in n-channel IGFET’S,” IEEE vol.sc-14,p442,1979
[2.4] B. eitan…et, ”Hot electron injection into oxide in n channel mos devices, IEEE Trans. Electron.
[2.5] Luca Larcher, Paolo Pavan, and Boaz Eitan, Senior Member, IEEE “On the Physical Mechanism of the NROM Memory Erase” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 10, OCTOBER 2004 1593
[2.6] San, K.T.; Kaya, C.; Ma, T.P.;” Effects of erase source bias on Flash EPROM device reliability” Electron Devices, IEEE Transactions on Volume 42, Issue 1, Jan. 1995 Page(s):150 – 159
[2.7] Steve S. Chung, Cherng-Ming Yih, Shui-Ming Cheng, and Mong-Song Liang “A New Technique for Hot Carrier Reliability Evaluations of Flash Memory Cell After Long-Term Program/Erase Cycles” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 9, SEPTEMBER 1999 1883
[2.8] Suk-Kang Sung, Il-Han Park, Chang Ju Lee, Yong Kyu Lee, Jong Duk Lee, Byung-Gook Park, Soo Doo Chae, and Chung Woo Kim “Fabrication and Program/Erase Characteristics of 30-nm SONOS Nonvolatile Memory Devices,” IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 2, NO. 4, DECEMBER 2003
[2.9] M.She, Tsu-Jae King, Senior Member, IEEE, Chenming Hu, Fellow, IEEE, Wenjuan Zhu, Zhijiong Luo, Jin-Ping Han, and Tso-Ping Ma, Fellow, IEEE ” JVD Silicon Nitride as Tunnel Dielectric in p-Channel Flash Memory” IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 2, FEBRUARY 2002 91
Chapter 4
[4.1] Suk-Kang Sung, Il-Han Park, Chang Ju Lee, Yong Kyu Lee, Jong Duk Lee, Byung-Gook Park, Soo Doo Chae, and Chung Woo Kim “Fabrication and Program/Erase Characteristics of 30-nm SONOS Nonvolatile Memory Devices,” IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 2, NO. 4, DECEMBER 2003
[4.2] R. Versari, A. Pieracci, D. Morig, B. Ricco, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 6, 2000
[4.3] William D.Brown, Joe E.brewer “Nonvolatile Semiconductor Memory Technology : A Comprehensive guide to understanding and using NVSMdevices,”,IEEE press. [4.4] Michael Hack, Alan G. Lewis, Senior Member, IEEE, and I-Wei Wu, Member, IEEE “Physical Models for Degradation Effects in Poly silicon Thin-Film Transistors” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40. NO. 5, MAY 1993
[4.5] N. D. Young: IEEE Trans. Electron Devices 43 (1996) 450.
[4.6] G. Tallarida, A. Pecora, G. Fortunato, F. Plais, P. Legagneux, T. Kretz
and D. Pribat: J. Non-Cryst. Solids 187 (1995) 195.
[4.7] G. Fortunato, A. Pecora, G. Tallarida, L. Mariucci, C. Reita and P. Migliorato: IEEE Trans. Electron Devices 41 (1994) 340.
[4.8] F. V. Farmakis, C. A. Dimitriadis, J. Brini, G. Kamarinos, V. K. Gueorguiev and T. E. Ivanov: Solid-State Electron. 43 (1999) 1259.
[4.9] Ching-Wei LIN, Chang-Ho TSENG, Ting-Kuo CHANG, Yuan-Hsun CHANG, Fang-Tsun CHU, Chiung-Wei LIN, Wen-Tung WANG and Huang-Chung CHENG, “An Investigation of Bias Temperature Instability in Hydrogenated Low-Temperature Polycrystalline Silicon Thin Film Transistors” Jpn. J. Appl. Phys. Vol. 41 (2002) pp. 5517–5522 Part 1, No. 9, September 2002 #2002 The Japan Society of Applied Physics
[4.10] Satoshi INOUE, Satoshi TAKENAKA1 and Tatsuya SHIMODA “Study of Degradation Phenomenon Due to a Combination of Contamination and Self-Heating in Poly-Si Thin Film Transistors Fabricated by a Low-Temperature Process” Jpn. J. Appl. Phys. Vol. 42 (2003) pp. 4213–4217 Part 1, No. 7A, July 2003
[4.11] Steve S. Chung, , Cherng-Ming Yih, Shui-Ming Cheng, and Mong-Song Liang “A New Technique for Hot Carrier Reliability Evaluations of Flash Memory Cell After Long-Term Program/Erase Cycles”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 9, SEPTEMBER 1999 1883