快閃記憶體為一非揮發性的記憶體，即儲存在其中的資料不會因為電源的移除而消失，而能維持一段很久的時間。而且因為其特殊的電荷注入機制，可以用簡單的方式達到寫入或是清除資料的效果。現今的3C 產品，手機、數位相機、MP3 player、隨身碟、記憶卡隨處都可以看到快閃記憶體的存在。隨著製程的進步，現在一片快閃記憶體晶片上可達8Gbit 的容量。如此大的容量可想像其測試時間和錯誤診斷的難度也隨著增加。若是有一套有系統的錯誤診斷和縮短測試時間的方法，不僅可以提高良率，也可以縮短測試成本。相關的問題是非常値得我們深入研究探討。
在這篇論文裡面，我們以錯誤型樣(fault pattern)為基礎進行快閃記憶體的錯誤診斷。我們建立一快閃記憶體的記憶體列陣模型，並植入缺陷模型加以模擬，來預測缺陷對快閃記憶體的影響。最後我們得到缺陷的錯誤型樣，並建立了快閃記憶體的缺陷對照庫。實驗結果證實利用這方法我們可以得到最高的診斷解析度。若是再配合電流測試(current testing)的方法，可以再進一步提高快閃記憶體的解析度。並且再進一步根據診斷的結果，縮短診斷方程式還可以節省診斷時間。
第二部份我們針對快閃記憶體的測試流程，提出一有系統的方法來縮短測試快閃記憶體時間。因為快閃記憶體的寫入模式比起隨機讀取記憶體花較長的時間，所以其測試方式不像隨機讀取記憶體一般有大量的重複寫入讀出動作。根據我們的方法，能在不減低其錯誤涵蓋率下，縮短快閃記憶體的測試時間。我們依照此一方法發展了一套自動化縮短測試快閃記憶體時間的工具。利用此自動化縮短測試時間工具在工業界快閃記憶體的測試流程上，有效的縮短了7%的測試時間。

Flash memory is a nonvolatile semiconductor memory which will not lose stored data after removed the power. Flash memory can be programmed or erased electrically on-line, and retains its stored data for a long time, so it is highly suitable for portable storage devices. Flash memory can be found everywhere in 3C products nowadays, for example, mobile phones, DSC, MP3 players, Flash disks, CF cards etc. The capacity of a single Flash memory chip can up to 8Gbit at present. With the increasing capacity, the test time becomes longer and failure analysis becomes more difficult. Thus, systematic methodologies of test time reduction and diagnosis will improve the yield and reduce the test cost for mass production.
In this thesis, we applied the diagnostic methodology that we developed for RAM to Flash memory, modifying as needed. Next, we built an electric model of Flash memory array, then injected defects and performed faulty circuits simulation by using a diagnostic test algorithm. After simulating faulty circuits, we use fault-pattern based diagnostic approach in Flash memory. Finally, we generated the defect dictionary of Flash memory. The resolution of our methodology reached 83.3% in NOR type Flash memory, and 100% in NAND type Flash memory.
Next, we proposed a systematic approach to reduce the test time of Flash memory. The test items of Flash memory are much different to RAM. It is because the write operations (erase and program) of Flash memory take a long time. To minimize the test time, there aren’t many Marchlike patterns applied in Flash memory test in industry. Based on our approach, we can reduce the test time without losing fault coverage. We developed an automatic test time reduction tool according to our methodology, and applied it to an industrial case to further reduce total test time by 7%.

[1] R. Dekker, F. Beenker, and L. Thijssen, “Fault modeling and test algorithm development for static random access memories,” in Proc. Int. Test Conf. (ITC), pp. 343–352, 1988.
[2] C.-W. Wang, K.-L. Cheng, J.-N. Lee, Y.-F. Chou, C.-T. Huang, C.-W. Wu, F. Huang, and H.-T. Yang, “Fault pattern oriented defect diagnosis for memories,” in Proc. Int. Test Conf. (ITC), (Charlotte), pp. 29–38, Sept. 2003.
[3] K.-L. Cheng, C.-W. Wang, J.-N. Lee, Y.-F. Chou, C.-T. Huang and C.-W. Wu, “FAME: a fault-pattern based memory failure analysis framework,” in Proc. IEEE/ACM Int. Conf.
Computer-Aided Design (ICCAD), (San Jose), pp. 595–598, Nov. 2003.
[4] A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice. Gouda, The Netherlands: ComTex Publishing, 1998.
[5] P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, Flash Memories. Boston: Kluwer Academic Publishers, 1999.
[6] J.-C. Yeh, C.-F. Wu, K.-L. Cheng, Y.-F. Chou, C.-T. Huang, and C.-W. Wu, “Flash memory built-in self-test using march-like algorithms,” in Proc. IEEE Int. Workshop on Electronic Design, Test, and Applications (DELTA), (Christchurch), pp. 137–141, Jan. 2002.
[7] K.-L. Cheng, J.-C. Yeh, C.-W. Wang, C.-T. Huang, and C.-W. Wu, “RAMSES-FT: A fault simulator for flash memory testing and diagnostics,” in Proc. IEEE VLSI Test Symp. (VTS), (Monterey, California), pp. 281–286, Apr. 2002.
[8] IEEE, IEEE 1005 Standard Definitions and Characterization of FloatingGate Semiconductor Arrays. Piscataway: IEEE Standards Department, 1999.
[9] P. Camurati, P. Prinetto, M. S. Reorda, S. Barbagallo, A. Burri, and D. Medina, “Industrial BIST of embedded RAMs,” IEEE Design & Test of Computers, vol. 12, pp. 86–95, Fall 1995.
[10] K. Zarrineh, S. J. Upadhyaya, and S. Chakravarty, “A new framework for generating optimal march tests for memory arrays,” in Proc. Int. Test Conf. (ITC), pp. 73–82, 1998.
[11] C.-T. Huang, J.-R. Huang, C.-F. Wu, C.-W. Wu, and T.-Y. Chang, “A programmable BIST core for embedded DRAM,” IEEE Design & Test of Computers, vol. 16, pp. 59–70, Jan.-Mar. 1999.
[12] C.-F. Wu, C.-T. Huang, and C.-W. Wu, “RAMSES: a fast memory fault simulator,” in Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT), (Albuquerque), pp. 165–173, Nov. 1999.
[13] M. G. Mohammad, K. K. Saluja, and A. Yap, “Testing flash memories,” in Proc. 13th Int. Conf. VLSI Design, pp. 406–411, Jan. 2000.
[14] M. G. Mohammad and K. K. Saluja, “Flash memory disturbances: modeling and test,” in Proc. IEEE VLSI Test Symp. (VTS), (Marina Del Rey, California), pp. 218 –224, Apr. 2001.
[15] S.-K. Chiu, J.-C. Yeh, C.-T. Huang, and C.-W. Wu, “Diagonal test and diagnostic schemes for flash memories,” in Proc. Int. Test Conf. (ITC), (Baltimore), pp. 37–46, Oct. 2002.
[16] C.-W. Wang, J.-R. Huang, Y.-F. Lin, K.-L. Cheng, C.-T. Huang, C.-W. Wu, and Y.-L. Lin,“Test scheduling of BISTed memory cores for SOC,” in Proc. 11th IEEE Asian Test Symp.
(ATS), (Guam), pp. 356–361, Nov. 2002.
[17] Y. E. Hong, L. S. Leong,W. Y. Choong, L. C. Hou, and M. Adnan, “An overview of advanced failure analysis techniques for Pentium and Pentium Pro microprocessors,” Intel Technology Journal, no. 2, 1998.
[18] J. Segal, A. Jee, D. Lepejian, and B. Chu, “Using electrical bitmap results from embedded memory to enhance yield,” IEEE Design & Test of Computers, vol. 15, pp. 28–39, May 2001.
[19] V. N. Yarmolik, Y. V. Klimets, A. J. van de Goor, and S. N. Demidenko, “RAM diagnostic tests,” in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), (San Jose), pp. 100–102, 1996.
[20] C.-F. Wu, C.-T. Huang, C.-W. Wang, K.-L. Cheng, and C.-W. Wu, “Error catch and analysis for semiconductor memories using March tests,” in Proc. IEEE/ACM Int. Conf. Computer-Aided Design (ICCAD), (San Jose), pp. 468–471, Nov. 2000.
[21] D. Niggemeyer and E. Rudnick, “Automatic generation of diagnostic March tests,” in Proc. IEEE VLSI Test Symp. (VTS), (Marina Del Rey, California), pp. 299–304, Apr. 2001.
[22] V. Vardanian and Y. Zorian, “A march-based fault location algorithm for static random access memories,” in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), (France), pp. 62–67, July 2002.
[23] C.-W. Wang, C.-F. Wu, J.-F. Li, C.-W. Wu, T. Teng, K. Chiu, and H.-P. Lin, “A built-in self-test and self-diagnosis scheme for embedded SRAM,” J. Electronic Testing: Theory and Applications, vol. 18, pp. 637–647, Dec. 2002.
[24] I. Schanstra, D. Lukita, A. J. van de Goor, K. Veelenturf, and P. J. van Wijnen, “Semiconductor manufacturing process monitoring using built-in self-test for embedded memories,” in Proc. Int. Test Conf. (ITC), (Washington, DC), pp. 872–881, Oct. 1998.
[25] J. T. Chen, J. Rajski, J. Khare, O. Kebichi, and W. Maly, “Enabling embedded memory diagnosis via test response compression,” in Proc. IEEE VLSI Test Symp. (VTS), (MarinaDel Rey, California), pp. 292–298, Apr. 2001.
[26] M. A. Merino, S. Cruceta, A. Garcia, and M. Recio, “SmartBitTM: bitmap to defect correlation software for yield improvement,” in Advanced Semiconductor Manufacturing Conference and Workshop, IEEE/SEMI, (Boston), pp. 194–198, Sept. 2000.
[27] Y.-T. Hsing, C.-W. Wang, C.-W. Wu, C.-T. Huang and C.-W. Wu, “Failure factor based yield enhancement for SRAM designs,” Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT), (Cannes), pp. 20–28, Oct. 2004.
[28] Kenneth V. Noren and Ming Meng, “Macromodel development for a FLOTOX EEPROM,”IEEE Tran. Electron Devices, vol. 45, pp. 224–229, Jan. 1998.
[29] Steve S. Chung, C.-M. Yih, S.S. Wu, H.H. Chen and Gary Hong, “A Spice-compatible flash EEPROM model feasible for transient and program/erase cycling endurance simulation,” in IEDM Tech. Dig., pp. 179–182, Dec. 1999.
[30] Mike O’Shea, Ann Concannon, Kevin McCarthy, Bill Lane, Alan Mathewson and Michiel Slotoom, “Development and application of a macro model for flash EEPROM design,” in
ASIC/SOC Conf.,2000. Proc. 13th Annual IEEE International, pp. 192–196, Sep. 2000.
[31] Luca Larcher, Paolo Pavan, Stefano Pietri, Lara Albani and Andrea Marmiroli, “A new compact DC model of floating gate memory cells without capacitive coupling coefficients,” IEEE Tran. Electron Devices, vol. 49, pp. 301–307, FEB. 2002.
[32] M. G. Mohammad and K. K. Saluja, “Electrical model for program disturb faults in nonvolatile memories,” in Proc. 16th Int. Conf. VLSI Design, (India), pp. 217–222, JAN. 2003.
[33] S. Hamdioui and A. J. van de Goor, “An experimental analysis of spot defects in SRAMs: realistic fault models and tests,” in Proc. Ninth IEEE Asian Test Symp. (ATS), (Taipei), pp. 131–138, Dec. 2000.
[34] C.-W. Wang, C.-F. Wu, J.-F. Li, C.-W. Wu, T. Teng, K. Chiu, and H.-P. Lin, “A built-in selftest and self-diagnosis scheme for embedded SRAM,” in Proc. Ninth IEEE Asian Test Symp. (ATS), (Taipei), pp. 45–50, Dec. 2000.
[35] W.-J. Wu, C.-Y. Tang, and M.-Y. Lin, “Methods for memory test time reduction,” in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), pp. 64–70, Aug. 1996.
[36] W.-J. Wu and C.-Y. Tang, “Memory test time reduction by interconnecting test items,” in IEEE Asian Test Symp. (ATS), pp. 290–298, Dec. 2000.
[37] S.-F. Kuo, J.-C. Yeh, C.-W. Wu and C.-H. Chen, “A systematic approach to semiconductor memory test time reduction,” in Proc. 15th VLSI Design/CAD Symp. (Pingtung), Aug. 2004.
[38] C.-F. Wu, C.-T. Huang, K.-L. Cheng, and C.-W. Wu, “Simulation-based test algorithm generation for random access memories,” in Proc. IEEE VLSI Test Symp. (VTS), (Montreal), pp. 291–296, Apr. 2000.