對於一個無線測試平台的測試資料通訊，測試資料無線傳輸是不可靠的，因此測試資料傳輸封包(Packet)將會加入錯誤更正碼(Error Correction)與重送資料封包的能力，測試工程師針對這類的通訊模組與待測電路(Device Under Test)的介面電路(Test Wrapper)設計是困難的，每一種待測試電路對於介面電路都有不同的需求，不能將介面電路作成 Hard Intellectual Properties (IPs)。我們提出自動化分析與合成測試介面電路，測試工程師只要透過一個測試描述語言，描述待測電路的測試操作(Test Operation)與測試向量(Test Pattern)。我們採用IEEE Standard (IEEE 1450.6) Core Test Language (CTL)來描述待測試電路，自動化分析與合成器可根據使用者的測試描述，產生符合使用者需求的介面電路與測試程式(Test Program)。測試介面電路之架構是使用模組化設計，它可用在不同的ATE Platform與待測電路不同的時脈速度(Clock Speed)，透過這個自動化合成分析器，不僅待測試電路可以在Wireless ATE Platform測試且具有Low Overhead 與讓使用者有最小的Design Effort。為了展示我們的成果，我們將使用現有的Wireless ATE Platform，在這個測試系統，測試介面電路提供一個無線通訊模組與DFT電路的介面轉換器，在論文中的實驗，我們展示自動化合成分析器針對各個DUT合成測試介面電路與測試程式。實驗結果顯示合成的測試介面電路大約在5.1K邏輯閘以下與4.3% Area Overhead。

In the event of unreliable test data communication, e.g. the wireless test system, packets with error correction and resent capability are preferred to encapsulate information. Yet, it is difficult for circuit/test designers to construct such test interface (or test wrapper) for this purpose. Also, it is inefficient to use hard Intellectual Properties (IPs) in this case, since every device under test
(DUT) have different requirements. One solution is to synthesize the wrapper automatically based in a description capable of characterizing the functionality of a DUT. In this thesis, we will use the IEEE standard (IEEE 1450.6) a.k.a. Core Test Language (CTL) to describe the test targets, and propose a synthesis tool to create wrappers for the target DUTs. In the meantime, the test program
run on testers can be generated automatically. The architectures of wrappers are modular to support
different ATE platforms (other than wireless channels), and they can be used in multiple clock
domains as well. Through the process, circuits can be tested with low overheads, and minimal
intervention from designers will be required.
The automation concept has been realized in this work. For demonstration purpose, we employed
a wireless test system as the target test platform. In such system, a test wrapper serves as
a bridge between communication modules and DFT circuits. In the experiments, we have demonstrated
that the proposed tool can synthesize the test wrapper as well as the test program automatically
for heterogeneous DUTs. As shown in experimental results, the area of synthesized test
wrappers are under 5.1k gates for the test cases with area overhead lower than 4.31%. Moreover,
an integrated chip has been tapped out which includes DUTs (memories), BIST, test wrappers and
communication modules (analog parts included).

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