鰭式場效電晶體介電質電阻式記憶體陣列的隨機電報雜訊之應力與溫度效應

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研究生：	陳致元 Chen, Chih-Yuan
論文名稱：	鰭式場效電晶體介電質電阻式記憶體陣列的隨機電報雜訊之應力與溫度效應 Stress and Temperature Effect on RTN Noise in FinFET Dielectric RRAM Array
指導教授：	林崇榮 Lin, Chrong-Jung
口試委員:	金雅琴施教仁
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering
論文出版年：	2019
畢業學年度：	107
語文別：	英文
論文頁數：	40
中文關鍵詞：	隨機電報雜訊、電阻式記憶體、退火
外文關鍵詞：	RTN, RRAM, Annealing
相關次數：	點閱：1 下載：0
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近年來，邏輯製程尺寸的迅速縮小提高了積體電路的特性與表現，隨之帶來許多對於現今製程方法與設計的挑戰與顧慮。許多原本微不足道的問題在科技節點繼續縮小的情況下，不能再被忽略；而隨機電報雜訊（Random Telegraph Noise，RTN）是其中之一。許多學者認真對待此問題，研究如何應對RTN所造成電路功能的改變及衰退；許多研究從縮小的元件上觀察RTN的表現，藉此探究RTN之特性及對電路、記憶體等元件的影響。
在本研究中，我們觀測鰭式場效電晶體介電質電阻式隨機存取記憶體 (FinFET Dielectric RRAM, FIND RRAM) 陣列的讀取電流中的RTN訊號。在元件接受反覆循環應力 (cycling stress) 下，其表現的RTN訊號也會隨之改變。這些明顯的RTN雜訊在FIND RRAM 元件經過高溫時被緩解，而且在高溫退火 (anneal) 之後有減輕且減少的趨勢。有了這些實驗觀察，此論文提出並示範一個晶載的退火機制，使得我們能夠在元件局部產生熱模擬加熱的情況已達到退火的效果，藉以修復因反覆循環應力所產生的缺損，進而延長元件的耐久度。

While rapid scaling of CMOS technology have improved the characteristics and performance of integrated circuits, it also raised challenges and concerns to existing methods and procedures. Many minor issues no longer remain minor as the device scales down the technology node, and Random telegraph noise (RTN) is one of them. Learning how to deal with RTN is a task many researchers partake in, and so it begins by examining the behavior of RTN signals in scaled devices.
In this work, an observation on RTN signals in the read current of a FinFET Dielectric RRAM (FIND RRAM) array is presented. The RTN signal of a FIND RRAM cell is found to change after the device endured cycling stress. After undergoing cycling stress, RRAM cells have a stronger tendency to show more RTN signals. The increased RTN noise in FIND RRAM cells can be alleviated generally by high temperature anneal. With this concept, an on chip annealing scheme involving locally heating the device to achieve annealing procedure is proposed and demonstrates.

摘要------------------------------------------------------i
Abstract--------------------------------------------------ii
Acknowledgement-------------------------------------------iii
List of Contents------------------------------------------iv
List of Figures-------------------------------------------vi
Chapter 1 Introduction------------------------------------1
1.1 Preface-----------------------------------------------1
1.2 Motivation--------------------------------------------2
1.3 Thesis Organization-----------------------------------3
Chapter 2 Review of FIND RRAM array and RTN---------------4
2.1 Review of FinFET Dielectric RRAM----------------------4
2.1.1 Device Structure Introduction-----------------------4
2.1.2 Electrical Properties-------------------------------5
2.2 Review of RTN-----------------------------------------6
2.2.1 Mechanism-------------------------------------------6
2.2.2 RTN Effect on Devices-------------------------------7
2.3 Summary-----------------------------------------------7
Chapter 3 Stress Effect on RTN in FIND RRAM Array---------14
3.1 Experiment Setup Introduction-------------------------14
3.2 Stressing the FIND RRAM via Cycling-------------------15
3.3 RTN Characteristic of a FIND RRAM Array---------------15
3.3.1 Fresh Cell RTN--------------------------------------15
3.3.2 Cycling Effect--------------------------------------16
3.4 Summary-----------------------------------------------17
Chapter 4 Temperature Effect in FIND RRAM Array-----------25
4.1 Temperature and Annealing Effect on RTN---------------25
4.1.1 Temperature effect on RTN---------------------------26
4.1.2 Annealing effect on RTN-----------------------------26
4.2 Recovery of Middle State Bits after Annealing---------27
4.3 On-Chip Annealing-------------------------------------28
4.4 Summary-----------------------------------------------28
Chapter 5 Conclusion--------------------------------------37
Reference-------------------------------------------------38

                                

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