一種使用分段電阻電容模型的方法來分析最大串音雜訊

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研究生：	張志豪 Chih-Hao Chang
論文名稱：	一種使用分段電阻電容模型的方法來分析最大串音雜訊 Modeling for Worst-case Crosstalk Noise Using Segmental RC Method
指導教授：	張慶元 Tsin-Yuan Chang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2004
畢業學年度：	92
語文別：	中文
論文頁數：	61
中文關鍵詞：	網路、串音雜訊、邏輯閘模型、極點/零點、最大串音雜訊
外文關鍵詞：	Interconnect, Crosstalk Noise, Gate Model, Pole / Zero, WCN
相關次數：	點閱：2 下載：0
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由於製程快速演進，元件的大小隨之快速縮小，而電路的性能也跟著加速。在現今的高速晶片中，網路(interconnect)上的延遲主宰了整個晶片性能。造成網路運作延遲或工作錯誤的因素中，串音雜訊(crosstalk noise)扮演了一個很重要的角色。在論文中將會對此現象做深入的探討，而且會對現今方法的優缺點做詳細的剖析。本論文目的即提供一個有效縮短分析時間及增加準確度的分析串音雜訊之方法。
由於之前所提出的方法皆用最簡單的模型去模擬邏輯閘部分，本篇論文提出了有效率的模型去模擬此部分，且透過本身發展的極點/零點分析程式可以大大的加速執行時間。在分析串音雜訊部份使用了分段電阻/電容方法，對於精確度而言增加非常多，在不失執行速度下能得到更精確的結果。
所有的例子分別使用提出的方法和其他方法做模擬並且加以比較，在比較之後發現提出的方法比用HSPICE軟體模擬方法較快，而其準確度(誤差<5%)也比以往方法的準確度高出許多，但在執行速度上面卻快上了幾十倍。如果能再針對演算法部份加以改進，相信執行速度一定會增加許多 (上百倍以上)。
我們所提出的方法可分析最大串音雜訊(Worst-case Crosstalk Noise WCN)，進而求出所相對應的輸入時間關係，這樣就可以知道何時才會發生最大串音雜訊。此外，未來我們將考慮電感元件和電感耦合的效應，以及找出更快速的演算法計算極點/零點分析以加快執行速度。之後更能對現有的積體電路做測試。

An analytical method for estimating crosstalk noise peak time, peak value and its corresponding input patterns is proposed in this thesis. Through self-written pole/zero analysis program, the transient analysis of interconnect structure is easily realized. Different from past modeling method, the single RC model for driver/receiver is replaced by segmental RC model for more accuracy. The method proposed here offers simulation results close to HSPICE simulations but execution time is much smaller. And the feature has the ability to deal with multi-line interconnect structures. Therefore, through proper alignment for aggressors produces input patterns that cause maximum crosstalk noise.

Abstract    1
Contents    2
List of Figures    4
List of Tables    6
Chapter 1 Introduction    7
1    Crosstalk Phenomena    9
2    Motivation    10
3    Organization    11
Chapter 2 Preliminaries    12
1    Worst-Case Crosstalk Noise (WCN)    12
1.1    The WCN Condition    12
1.2    Aggressor Alignment    13
2    Asymptotic Waveform Evaluation (AWE )    14
2.1    Moment Generation    14
2.2    Moment Matching    15
3    Numerical Methods    17
3.1    Newton Method and Modified False Position Method    17
3.2    Companion Matrix and QR Iteration    18
4    Gate Modeling    21
4.1    Inverter Gate Model    21
4.2    Analysis of Parameters    22
4.3    Input and Output Relationship    23
Chapter 3 The Proposed Analysis Flow    25
1    Construction of Interconnect Structure    25
1.1    Input Signal Information    27
1.2    Combine With Inverter Model    28
2    Generate Transfer Functions    30
2.1    Polynomial Generation    30
2.2    Model Reduction    31
2.3    Pole / Zero Generation    33
3    Estimate Peak Time    35
3.1    Pole Approximation Method    36
3.2    AWE Technique for Initial Value    37
3.3    Segmental RC Model    37
3.4    Estimate Peak Time Flow    41
3.5     Aggressor Alignment    44
Chapter 4    Simulation Results and Comparisons    47
1    Simulation Conditions    47
1.1    Pole / Zero Constraints    47
2    Simulation Results    49
2.1    Pre-work Preparations    50
2.2    Real Case Simulations    54
Chapter 5 Conclusions    58
Bibliography    59

                                

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