40Gbps超高速虛擬輸出佇列之設計與實作｜國立清華大學博碩士論文庫

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研究生：	蔡世敏 Tsai, Shih Min
論文名稱：	40Gbps超高速虛擬輸出佇列之設計與實作 Design and Implementation of 40Gbps Ultra High Speed VOQ
指導教授：	李端興 Lee, Duan Shin
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2009
畢業學年度：	97
語文別：	中文
論文頁數：	46
中文關鍵詞：	虛擬輸出佇列
外文關鍵詞：	Virtual Output Queue
相關次數：	點閱：3 下載：0
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Input Buffer Switch現在已經被廣泛的應用在各級網路交換機中，然而他會遇到的一個嚴重問題就是Head of Line Blocking，這個問題會大幅降低交換機的Throughput。虛擬輸出佇列(Virtual Output Queue)可以解決這個問題，然而現在既有的VOQ設計並不足以應付未來高速的40 Gbps網路。

在本篇論文中，我們參考了之前光纖延遲線的相關研究成果，在去年本團隊實做過的超高速先進先出佇列上進行架構修改。一方面保存了高容量且高速的特性，並加入了動態記憶體位址配置，新的記憶體存取機制，擴充成多重佇列等新觀念，作出一個高速而且高容量的虛擬輸出佇列。它具有VOQ的一切特點，並且還有高存取速率和高儲存容量兩項優勢，可以與未來高速交換機相互配合。

摘要    I
CONTENTS    II
FIGURES    V
CHAPTER1  MOTIVATION AND INTRODUCTION    1
CHAPTER2  FEATURES AND INNOVATION OF OUR DESIGN    3
1 INTEGRATE COMPLEMENTARY MEMORY CHARACTERISTICS TO REALIZE HIGH SPEED VOQ    3
2 APPLY OPTICAL THEORY RESULT TO DEVELOP PRACTICAL AND SCALABLE HIGH SPEED VOQ ARCHITECTURE    3
3 REALIZE HIGH SPEED VOQ TO ACHIEVE 40GBPS DATA FLOW    4
4 HIGH SPEED, LARGE CAPACITY, AND ECONOMICAL PRICE    4
5 3-HIERARCHY PACKET BUFFERING ARCHITECTURE    4
6 HIGH SCALABLE AND 高度擴展性及可調控性    5
7利用動態鏈結串列(LINK LIST)讓FIFO升級為VOQ    5
CHAPTER3  CHALLENGES AND DESIGN SOLUTIONS    6
1 PRELIMINARY    6
1.1 VOQ Introduction    7
1.2 Time Interleaving Property and Scaling Factor    8
2 CHALLENGES    10
2.1 No Fast Enough High Speed Memory Device to Support 40Gbps    10
2.2 No Electrical High Speed VOQ Architecture to Support 40Gbps using Low Speed Memory    10
2.3 Convert Optical Queueing Architecture to Electrical Feasible High Speed Architecture    11
2.4 Traditional VOQ Buffer Management Requires Modification    11
3 DESIGN SOLUTIONS    12
3.1 Parallel FIFO Queues with Switched Delay Lines Review    12
3.2 4-Port Device Reduction    13
3.3 Time Interleaving Backward Expansion    15
3.4 Periodic Round-robin to Compensate Long Latency    16
3.5 DRAM Bandwidth Calculation    17
3.6 Replace Optical Cell with SDRAM    18
3.7 Additional Cache to Prevent Memory Auto-referesh    21
3.8 Link List Management for Memeory Allocation    22
CHAPTER 4 SYSTEM ARCHITECTURE    24
1 ASSUMPTION    24
2 SYSTEM OPERATION    24
2.1 Dump Path Operation Illustration    25
3 HARDWARE DESIGN    26
3.1 Packet Generator    27
3.2 Boundary Detector    27
3.3 High Speed Queue    28
3.4 Flow Splitter    28
3.5 Aurora SerDes Interface    28
CHAPTER 5 IMPLEMENTATION OF HIGH SPEED VOQ    29
1 MAIN ARCHITECTURE    29
2 PATH SWITCHING MODULE    29
2.1 Packet Loss Path Switch    29
2.2 Dump Packet Store Path Switch    29
2.3 Dump Packet Retrieve Path Switch    30
2.4 Head Q Storage    30
2.5 Tail Q Storage    31
2.6 Dump Decision Module    31
3 MEMORY ACCESS MODULE    33
3.1 Dump Module    34
3.2 Buffer Manager Module    35
CHAPTER6 EXPERIMENT RESULT    36
1 ENVIRONMENT FOR EXPERIMENT     36
2 PATH SWITCHING MODULE    36
3 MEMORY ACCESS MODULE     39
CHAPTER 7 CONCLUSIONS    45

                                

[1] C.-S. Chang, D.-S. Lee and C.-K. Tu, “Recursive construction of FIFO optical multiplexers with switched delay lines,” IEEE Transactions on Information Theory, Vol. 50, pp. 3221-3233, 2004.
[2] Po-Kai Huang, Cheng-Shang Chang, Jay Cheng and Duan-Shin Lee, "Recursive constructions of parallel FIFO and LIFO queues with switched delay lines," IEEE Transactions on Information Theory, Vol. 53, 1778-1798, 2007.
[3] http://www.oiforum.com/public/documents/OIF-SFI5-01.0.pdf, System Interface Level (SxI-5): Common Electrical Characteristics for 2.488-3.125Gbps Parallel Interfaces, 2002.

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