研究生: |
高珍 Kao, Chen |
---|---|
論文名稱: |
以人因工程觀點改善查核表之實用性: 以矽智財開發流程為例 An Ergonomics Study on Improving the Checklists Effectiveness- Using the Flow of Silicon IP Development as an Example |
指導教授: |
王明揚
Wang, Eric |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
工學院 - 工業工程與工程管理學系碩士在職專班 Industrial Engineering and Engineering Management |
論文出版年: | 2011 |
畢業學年度: | 99 |
語文別: | 中文 |
論文頁數: | 80 |
中文關鍵詞: | 矽智財 、查核表 、人為失誤 |
外文關鍵詞: | Silicon Intellectual Property, Checklist, Human Error |
相關次數: | 點閱:2 下載:0 |
分享至: |
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對於晶圓代工產業而言,如何提供多元化且品質具有競爭力的矽智財(Silicon Intellectual Property, 以下簡稱SIP),以吸引更多客戶投片生產,對於晶圓代工廠在市場上的競爭地位有相當大的影響。影響SIP品質的因素相當多,人為失誤在開發或品管流程上,是無法避免卻又發生頻繁的根本因素,常見的改善手法有教育訓練、系統防呆機制、改善工作環境等,但業界常用的手法為查核表(Checklist)之使用。
查核表的使用範圍相當廣泛,許多研究也發展出各式各樣之查核表來符合不同產業之需求,以避免人為因素造成作業上的失誤。但針對SIP研發設計流程之查核表資料做進一步分析之後,發現實務上並無發揮該有的效能,表單不是過於簡單,未將關鍵因素列入考量;就是過於冗長,造成工程師額外的工作負荷。探究原因後發現,該查核表的設計並未考量人因工程的觀點,針對關鍵影響流程及可能發生人為失誤的步驟加強檢視。相反的,管理者往往只為紙上作業而非徹底改善角度來執行,不了解人為失誤所造成的嚴重性,造成投入改善資源的不足,也增加許多不必要的機會成本。
本研究以晶圓代工廠矽智財研發暨設計支援處為研究對象,針對SIP開發流程使用之查核表,探討管理者應注重的潛在人為因素。藉由使用者問卷分析搭配深度訪談,列出可能產生人為失誤之關鍵因子,並納入人因工程觀點修改查核表,使工程師能確實掌握現有研發流程中可能發生的潛在性人為失誤,有效防範人為失誤的發生。
關鍵詞: 矽智財(Silicon Intellectual Property)、查核表(Checklist)、人為失誤(Human Error)
Being able to provide a diverse range of products with superior quality of the Silicon Intellectual Property (hereafter referred to as SIP) serves as a competitive advantage for any semiconductor foundry. There are many factors that may influence the quality of SIPs. Among them, the human errors on the product development and assurance procedure are inevitable and frequently seen; they are in fact the root cause of many problems. The commonly used techniques for improvement including education and training, an introduction of mistake-proofing mechanism, and the enhancement of work environment, etc. However, the most widely applied technique is the usage of checklists.
Checklists may be applied in an extensive scope. Researches have also developed a variety of checklists according to the different demands from different industries aiming to prevent any negative outcome caused by human errors. However, the results found from this practical analysis on the checklists of SIP development cycle shows that the forms are either too simple to include the key factors or tediously long which impacts the workload of engineers. By studying into the problems, it is found that not only the ergonomic factors have not been considered carefully in designing the original checklists but the key steps that often involved with human errors also are not being reinforced. In contrary, managers tend to focus more on just the paper work, and merely on the improvement to lessen the human errors. The impact of human errors and its severity are not well understood or seen; thus, the resources devoted for further improvements are often insufficient and the unnecessary opportunities costs are wasted.
This research has taken an Intellectual Property Design Department of a wafer foundry as the subject of study. The focus is to examine the checklists of SIP development flow, and analyze the potential human factors, which should be emphasized by the managers. The possible key factors are derived and summarized from the study of questionnaires and in-depth personal interviews. The modified checklists with those human factors taking into consideration can now help engineers to well control the potential human errors and effectively prevent the occurrence of such errors during the process of research and development.
Keywords: Silicon Intellectual Property、Checklist、Human Error
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