近幾年製程的持續演進，從180nm、90nm、65nm、40nm到目前的28nm。元件尺寸不斷的縮小，但製程變異對電路效能的影響卻日趨嚴重，在電路設計上直接影響到產品的良率降低。為了在設計階段先行觀察元件製程變異的影響，設計者通常會透過蒙地卡羅的統計分析方法，在電路模擬中將元件變異的資訊考慮進去。然而，直接在模擬軟體(如:HSPICE、SPECTRE)中，應用統計的方法描述參數變異做電路分析，是相當的耗費時間，甚至對較大型的電路而言，這可能是無法實行的模擬方式。類比電路設計中，相當重視實體佈局上元件的匹配，因此特別在意製程變異所帶來的影響。常使用共質心方法來消除元件之間不匹配的現象。然而，這些規則只能用於佈局時的參考準則，並無一個客觀的方式來量化匹配程度。元件之間的繞線，無法避免的也會造成寄生效應，元件尺寸的製程變異、實體佈局的匹配設計、寄生效應的影響，這些都是可能造成產品良率降低的因素。

本論文提出了一套快速的考慮製程變異的良率預估及佈局評估軟體，我們將變異分成，元件本身的變異、與實體佈局相關的變異分佈、寄生效應等，三個層次。每個層面我們都採用蒙地卡羅的統計分析方法來預估變異所造成的影響。在我們所提出的軟體YARLO中，我們將協助設計者方便使用製程廠提供的變異資訊，半自動化的進行蒙地卡羅分析。在模擬過程中將改變蒙地卡羅單純隨機分佈的性質，提倡使用變異梯度模型，更切實際的考慮製程變異的影響。採用平行處理的概念撰寫軟體，且提供友善的操作介面(GUI)，實現方便操作且速度較快的蒙地卡羅分析。在YARLO中可以執行與佈局相關(Layout Dependent)的模擬，使設計者能在模擬階段便得知布局設計的好壞。在設計流程中的前段我們就能幫助設計者考慮了製程變動的影響，除了可以讓使用者方便使用製程廠提供的變異資訊以及減少設計者進行模擬的時間，也可以避免設計者面臨過度設計或者降低需要調整設計的機率。如此一來便可縮短整個設計流程，降低設計成本。最重要的是產品良率的提升。

As technological process continue to evolve in recent years, from 180nm, 90nm, 65nm, 40nm until 28nm, while the dimension of device keeps on shrinking. However, process variations have a large impact on circuit performance by decreasing the rate of the product’s yield. While designing the early stage of circuit design, designers want to observe the effects of process variations using the Monte Carlo statistical analysis, which takes the device variations of circuit simulation into consideration. Nevertheless, it takes a lot of time to analyze the statistics of circuit in simulators such as HSPICE or SPECTRE, and even impossible for large circuits. In analog circuits, device matching of physical layout is very pivotal and we very concern the effects of process variation. Designers often use common-centroid to eliminate device mismatches. Nonetheless, these principles are only for reference during physical layout and do not follow an objective standard measurement. The parasitic effect of routing between devices is inevitable. The variation of device dimension, the matching arrangement of physical layout, and the parasitic effect of routing are factors that might cause the circuit’s yield to decrease.
This thesis provides fast yield estimation software within the consideration of process variation. We can classify variations into three aspects: the variation of device dimension, the variation dependent on physical layout, and the parasitic effect. For each aspect, we use the Monte Carlo simulation to predict the effects of process variations. Moreover, our software achieves a faster version of Monte Carlo simulation. Therefore, we can have an efficient way of estimating the yield from three different aspects in the early stage of design, thereby providing designers with a choice when choosing the size of the device and layout arrangement. Hence, we can avoid redesigning the circuit or rearranging the physical layout. Other than to lower the cost of designing the product, we can improve the time to market.

[1] K. Chang, “Accurate on-chip variation modeling to achieve design for manufacturability,” Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC), Banff, Canada, pp. 219-222, July 2004.
[2] K. Doong et al., “4K-ceels Resistive and Charge-Base-Capacitive Measurement Test Structure Array (R-CBCM-TSA) for CMOS Logic Process Development, Monitor and Model,” Proceedings of ICMTS, 2009.
[3] C. Cho, D. Kim, J. Kim, J. -O. Plouchart, and R. Trzcinski, “Statistical framework for technology-model-product co-design and convergence,” in Proc. of International Conference on Computer-Aided Design, pp. 503–508, 2007.
[4] H. Masuda, S. Ohkawa, A. Kurokawa, M. Aoki, “Challenge: Variability characterization and modeling for 65-to 90-nm processes,” in Proc. of IEEE Custom Integrated Circuits Conference, pp. 593 – 599, 2005.
[5] M. J. Pelgrom, A. C.Duinmaijer, A. P. Welbers, “Matching properties of MOS transis-tors,” IEEE J. Solid State Circuits, vol. 24, pp. 1433-1440, Oct. 1989.
[6] 張克正/唐經洲 譯(Chiang), 奈米CMOS電路可生產性與良率設計(Chiang:Design for Manufacturability & Yield for Nano-Scale CMOS), 滄海書局, 2010年.
[7] T. E. Gbondo-Tugbawa, “Chip-Scale modeling of pattern dependencies in copper chemical mechanical polishing process,” Ph.D. dissertation, Massachusetts Institute of Technology, 2002.
[8] B.E. Stine, D.S. Boning and J.E. Chung, “Analysis and decomposition of spatial variation in integrated circuit processes and devices,” IEEE Transactions on Semiconductor Manufacturing, 10(1), pp. 24-41, 1997.
[9] X. Jinjun, V. Zolotov, and H. Lei, “Robust extraction of spatial correlation,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 4, pp. 619-631, April 2007.
[10] D. Sayed and M. Dessouky, ”Automatic generation of Common-Centroid arrays with arbitrary capacitor ratio,” in Proc. of Design, Automation and Test in Europe Conference and Exhibition, pp. 576-580, 2002.
[11] A. Maxim, M. Gheorghe, “A novel physical based model of deep-submicron CMOS transistors mismatch for Monte Carlo SPICE simulation,” in Proc. of International. Symposium on Circuits and Systems, pp. 511-514, 2001.
[12] P. G. Drennan, C. C. McAndrew, and J. Bates, “A comprehensive vertical BJT mis-match model,” Proc. IEEE BCTM, pp. 83-86, Oct. 1998.
[13] [Online]. Available : http://140.115.71.96/wiki3/index.php/Process_Variation_and_Modeling
[14] D.A. John and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, New York, 1997.
[15] NTHU CS5152 Workshop in VLSI design handout