三維積體電路相對於二維積體電路而言有許多優點，如更短的全域線
長和較佳效能。模組元件與矽晶穿孔(Through-Silicon Via)的位置
在決定線長時扮演了重要的角色。我們使用疊代法在白空間重新分配
來改善全域線長。在每個改善步驟中我們建立並更新約束圖，白空間
重新分配被制定成兩組線性規劃(Linear Programming)並被最新發
展的解算器所解決。實驗數據顯示在所有的測試裡該演算法可以達到
最高7.3%的線長縮短並只花費少量時間。

Three dimensional integrated circuit (3-D IC) technique has various of benefits compared to traditional two dimensional IC (2D-IC) such as shorter global interconnect and higher performance. Positions of module blocks and Through-Silicon-Vias(TSV) plays an important role in total wirelength. To reduce the total wirelength, we use an iterative white space
redistribution algorithm to improve the global interconnect. Constraint graph is constructed and updated during each refinement step, the whitespace redistribution is formulated as two linear programs and solved by an state-of-the-art optimizer. The experimental result shows the algorithm can achieve at most 7.3% wirelength reduction over all testcases and the runtime is very fast.

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