以先進電信運算架構為基礎的負載平衡布可夫范紐曼交換機之VOQ儲存緩衝器與重組儲存緩衝器位址管理之設計與實作

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研究生：	顏苑如 Yuen-Ru Yen
論文名稱：	以先進電信運算架構為基礎的負載平衡布可夫范紐曼交換機之VOQ儲存緩衝器與重組儲存緩衝器位址管理之設計與實作 Address Management of VOQ and Re-sequencing Buffers in AdvancedTCA based Load Balanced Birkhoff-von Neumann Switches
指導教授：	李端興 Duan-Shin Lee
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 通訊工程研究所 Communications Engineering
論文出版年：	2008
畢業學年度：	96
語文別：	英文
論文頁數：	77
中文關鍵詞：	交換機、布可夫范紐曼、VOQ 、重組
相關次數：	點閱：1 下載：0
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現今的網際網路蓬勃發展，但在網路封包的傳輸上仍無法達到百分之百的效能。由於封包在傳送時無法事先知道封包大小，也無法事先知道封包的傳輸速率，以至於無法準確決定封包的傳輸路徑，導致封包可能在途中被丟棄或是封包延遲太久才傳送到目的端…等等的問題。於是理論上提出了負載平衡布可夫范紐曼這個方法，這個方法即使無法事先知道封包大小也可以實作，當封包到達輸入端後直接將封包切割成固定大小，由第一級交換機做平均分配的傳輸，再透過第二級交換機經過重組將封包傳出，而這過程中交換機的傳輸路徑便是由布可夫范紐曼演算法決定。透過兩級交換機與負載平衡布可夫范紐曼演算法的搭配，這就是我們所實作交換機的基本架構。在本論文中，我們組織一個團隊在先進電信運算架構(AdvancedTCA)的平台上去實作一個以負載平衡布可夫范紐曼交換機為基礎的架構，依此架構為基礎提出一些設計上的創新，雖然繼承了此交換機的一些優點，但也面臨了一些挑戰，因此也提出的相對應的解決方案來解決這些問題。在最後我們也藉由實驗結果驗證該交換機的功能，它不僅確實能達到100%的效能，也增加了交換機的擴充性，並降低了硬體複雜度，且在高負載和爆發流量是有低平均延遲的表現，還能有效的使用暫存器。

摘要        I
前言        II
CONTENTS        III
CHAPTER 1    MOTIVATION AND INTRODUCTION    1
1.    INTRODUCTION    2
2.    OUTLINE OF THIS PROPOSAL    3
CHAPTER 2    FEATURES AND INNOVATION OF OUR DESIGN    5
1.    INHERIT THE BENEFITS FROM LOAD-BALANCED BIRKHOFF-VON NEUMANN SWITCH    5
2.    FOLDED ARCHITECTURE TO REDUCE CENTRALIZED VOQ BUFFER COMPLEXITY    5
3.    SWITCHING LEVEL PARALLELISM TO RESTORE 100% THROUGHPUT    5
4.    RELIEF OF ORIGINAL SHORT DISTANCE VARIATION CONSTRAINT    6
5.    3-LEVEL HIERARCHY VOQ BUFFER DESIGN TO FIT PIPELINE TIMING BUDGET    6
6.    ADDITIONAL RE-SEQUENCE BUFFER TO SIMPLIFY CELL REASSEMBLY    7
7.    FAULT-TOLERANT SWITCH FABRIC TO PREVENT UNRECOVERABLE REASSEMBLY    7
8.    PROTOTYPE CREATED BASED ON STANDARD ADVANCEDTCA PLATFORM    8
CHAPTER 3    CHALLENGES AND DESIGN SOLUTIONS    9
1.    PRELIMINARY    9
1.1.    Cell Transmission Time    9
1.2.    SerDes Channel Latency    11
2.    CHALLENGES    12
2.1.    Central VOQ Buffer Complexity Limits Scalability    13
2.2.    Long Transmission Latency Limits Throughput    13
2.3.    Synchronization Restrains Propagation Distance Variation    13
2.4.    Traditional VOQ Buffer Management Requires Speedup    14
2.5.    Out-of-Order Transmission Makes Reassembling Difficult    15
2.6.    Faulty Linecard Makes Permanent Unrecoverable Reassembly    15
3.    DESIGN SOLUTIONS    16
3.1.    Folded Architecture Design    16
3.2.    Switching Level Parallelism    19
3.3.    Synchronization Analysis    22
3.4.    Synchronization Analysis    25
3.5.    Re-sequence Buffer Design    30
3.6.    Fault Tolerant Design    33
CHAPTER 4    SYSTEM ARCHITECTURE    44
1.    ASSUMPTION    45
2.    HARDWARE DESIGN    46
2.1.    Linecard Blade Design    47
2.2.    Switch Fabric Blade Design    49
2.3.    Stand-alone switch integration    50
3.    SYSTEM OPERATION    52
3.1.    Ingress Process    52
3.2.    First Stage Switch    53
3.3.    VOQ Buffer    54
3.4.    Second Stage Switch    55
3.5.    Re-sequencing Buffer    56
3.6.    Egress Process    57
CHAPTER 5    FPGA IMPLEMENTATION    59
1.    INTRODUCTION OF SRAM    59
2.    IMPLEMENT OF VOQ BUFFER    62
2.1.    Init of VOQ buffer    63
2.2.    En-queue of VOQ buffer    64
2.3.    De-queue of VOQ buffer    67
3.    IMPLEMENT OF RE-SEQUENCING BUFFER    69
3.1.    Init of re-sequencing buffer    70
3.2.    En-queue of re-sequencing buffer    72
3.3.    De-queue of re-sequencing buffer    73
CHAPTER 6    CONCLUSION    75
REFERENCES    76

                                

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