隨著製程越來越進步，對電路的功能需求也變得越來越複雜。靜態時序
分析是設計電路流程中重要的一環，但在複雜的電路中進行時序分析會非
常耗時。目前其中一個主流的方式是使用階層式的設計流程來加快電路時
序分析與完成時序限制的時間。在本文中我們提出了一個高精準度萃取式
時序模型，可以用在階層式設計流程中來加快靜態時序分析。介面式時序
模型(interface logic model) 與萃取式時序模型(extracted timing model) 是目前兩個主流的時序模型。前者精準度非常高，但相對萃取式而言模型大小比
較大；萃取式的優勢在於擁有非常小的模型大小，但有著在一些情況下精
確度不高的缺點。最近的研究試著在縮小介面式時序模型下保持模型的準
確性。但是與萃取式時序模型相比，他們的模型大小仍然相對較大，進而
影響模型的使用效率。我們基於萃取式時序模型，在不增加太多模型大小
下，試著改善其精準度的問題。我們使用2017 TAU Timing Contest 的測資
來測量我們的模型效能。實驗結果顯示我們可以有效地降低萃取式時序模
型的誤差，平均而言誤差可以從102皮秒降低到1皮秒以下。與介面式時序
模型相比，我們準確度的差也在1皮秒以下，但可以擁有最高270倍小的模
型。

As technology advances, the complexity and size of integrated circuits continue to grow. Hierarchical design flow is a mainstream solution to speed up timing closure. Static timing analysis is a pivotal step in the flow but it can be timing-consuming on large flat designs. To reduce the long runtime, we introduce ATM, a high-accuracy extracted timing model for hierarchical timing analysis. Interface logic model (ILM) and extracted timing model (ETM) are the two popular paradigms for generating timing macros. ILM is accurate but large in model size, and ETM is compact but less accurate. Recent research has applied graph compression techniques to ILM to reduce model size with simultaneous high accuracy. However, the generated models are still very large compared to ETM, and its efficiency of in-context usage may be limited. We base ATM on the ETM paradigm and address its accuracy limitation. Experimental results on TAU 2017 benchmarks show that ATM reduces the maximum absolute error of ETM from 102 ps to less than 1 ps. Compared to the ILM-based approach, our accuracy differs within 1 ps and the generated model can be up to 270× smaller

[1] A. J. Daga, L. Mize, S. Sripada, C. Wolff, and Q. Wu, “Automated timing model generation,” DAC ’02, p. 146–151, 2002.
[2] “Liberty user guides and reference manual suite.” https://www. opensourceliberty.org/.
[3] P.-Y. Lee, I. H.-R. Jiang, and T.-Y. Yang, “iTimerM: Compact and Accurate Timing Macro Modeling for Efficient Hierarchical Timing Analysis,” ISPD ’17, p. 83–89, 2017. [4] T.-Y. Lai, T.-W. Huang, and M. D. F. Wong, “LibAbs: An Efficient and Accurate Timing Macro-Modeling Algorithm for Large Hierarchical Designs,” in Proceedings of the 54th Annual Design Automation Conference 2017, DAC ’17, 2017.
[5] T.-Y. Lai and M. Wong, “A highly compressed timing macro-modeling algorithm for hierarchical and incremental timing analysis,” in 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 166–171, 2018.
[6] Y. Yang, Y. Chang, and I. H. Jiang, “iTimerC: Common path pessimism removal using effective reduction methods,” in 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 600–605, 2014.
[7] S. Zhou, Y. Zhu, Y. Hu, R. Graham, M. Hutton, and C.-K. Cheng, “Timing model reduction for hierarchical timing analysis,” ICCAD ’06, p. 415–422, 2006.
[8] “TAU 2017 Timing Contest on Macro Modeling,” 2017. https:// sites.google.com/site/taucontest2017/.
[9] T.-W. Huang and M. Wong, “OpenTimer: A high-performance timing analysis tool,” in 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 895–902, Nov 2015.
[10] C. V. Kashyap, C. J. Alpert, F. Liu, and A. Devgan, “Closed-form expressions for extending step delay and slew metrics to ramp inputs for rc trees,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 509–516, 2004.